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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4353-drm-amd-display-compact-the-rq-dlg-ttu-log.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/4353-drm-amd-display-compact-the-rq-dlg-ttu-log.patch390
1 files changed, 390 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4353-drm-amd-display-compact-the-rq-dlg-ttu-log.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4353-drm-amd-display-compact-the-rq-dlg-ttu-log.patch
new file mode 100644
index 00000000..b979adfe
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4353-drm-amd-display-compact-the-rq-dlg-ttu-log.patch
@@ -0,0 +1,390 @@
+From 04151c4a461ca0336af26b19039f63923239b76e Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 11 Apr 2018 11:51:32 -0400
+Subject: [PATCH 4353/5725] drm/amd/display: compact the rq/dlg/ttu log
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 4 +-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 24 ++-
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 235 +++++++++------------
+ drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 22 +-
+ 4 files changed, 128 insertions(+), 157 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+index 759fcd1..159bebc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+@@ -763,10 +763,10 @@ void min_set_viewport(
+ PRI_VIEWPORT_Y_START_C, viewport_c->y);
+ }
+
+-void hubp1_read_state(struct hubp *hubp,
+- struct dcn_hubp_state *s)
++void hubp1_read_state(struct hubp *hubp)
+ {
+ struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
++ struct dcn_hubp_state *s = &hubp1->state;
+ struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
+ struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
+ struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+index 02045a8..fe9b8c4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+@@ -619,8 +619,29 @@ struct dcn_mi_mask {
+ DCN_HUBP_REG_FIELD_LIST(uint32_t);
+ };
+
++struct dcn_hubp_state {
++ struct _vcs_dpi_display_dlg_regs_st dlg_attr;
++ struct _vcs_dpi_display_ttu_regs_st ttu_attr;
++ struct _vcs_dpi_display_rq_regs_st rq_regs;
++ uint32_t pixel_format;
++ uint32_t inuse_addr_hi;
++ uint32_t viewport_width;
++ uint32_t viewport_height;
++ uint32_t rotation_angle;
++ uint32_t h_mirror_en;
++ uint32_t sw_mode;
++ uint32_t dcc_en;
++ uint32_t blank_en;
++ uint32_t underflow_status;
++ uint32_t ttu_disable;
++ uint32_t min_ttu_vblank;
++ uint32_t qos_level_low_wm;
++ uint32_t qos_level_high_wm;
++};
++
+ struct dcn10_hubp {
+ struct hubp base;
++ struct dcn_hubp_state state;
+ const struct dcn_mi_registers *hubp_regs;
+ const struct dcn_mi_shift *hubp_shift;
+ const struct dcn_mi_mask *hubp_mask;
+@@ -698,8 +719,7 @@ void dcn10_hubp_construct(
+ const struct dcn_mi_shift *hubp_shift,
+ const struct dcn_mi_mask *hubp_mask);
+
+-void hubp1_read_state(struct hubp *hubp,
+- struct dcn_hubp_state *s);
++void hubp1_read_state(struct hubp *hubp);
+
+ enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 5e7498e..fe52cbc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -112,143 +112,127 @@ void dcn10_log_hubbub_state(struct dc *dc)
+ DTN_INFO("\n");
+ }
+
+-static void print_rq_dlg_ttu_regs(struct dc_context *dc_ctx, struct dcn_hubp_state *s)
+-{
+- struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
+- struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
+- struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
+-
+- DTN_INFO("========Requester========\n");
+- DTN_INFO("drq_expansion_mode = 0x%0x\n", rq_regs->drq_expansion_mode);
+- DTN_INFO("prq_expansion_mode = 0x%0x\n", rq_regs->prq_expansion_mode);
+- DTN_INFO("mrq_expansion_mode = 0x%0x\n", rq_regs->mrq_expansion_mode);
+- DTN_INFO("crq_expansion_mode = 0x%0x\n", rq_regs->crq_expansion_mode);
+- DTN_INFO("plane1_base_address = 0x%0x\n", rq_regs->plane1_base_address);
+- DTN_INFO("==<LUMA>==\n");
+- DTN_INFO("chunk_size = 0x%0x\n", rq_regs->rq_regs_l.chunk_size);
+- DTN_INFO("min_chunk_size = 0x%0x\n", rq_regs->rq_regs_l.min_chunk_size);
+- DTN_INFO("meta_chunk_size = 0x%0x\n", rq_regs->rq_regs_l.meta_chunk_size);
+- DTN_INFO("min_meta_chunk_size = 0x%0x\n", rq_regs->rq_regs_l.min_meta_chunk_size);
+- DTN_INFO("dpte_group_size = 0x%0x\n", rq_regs->rq_regs_l.dpte_group_size);
+- DTN_INFO("mpte_group_size = 0x%0x\n", rq_regs->rq_regs_l.mpte_group_size);
+- DTN_INFO("swath_height = 0x%0x\n", rq_regs->rq_regs_l.swath_height);
+- DTN_INFO("pte_row_height_linear = 0x%0x\n", rq_regs->rq_regs_l.pte_row_height_linear);
+- DTN_INFO("==<CHROMA>==\n");
+- DTN_INFO("chunk_size = 0x%0x\n", rq_regs->rq_regs_c.chunk_size);
+- DTN_INFO("min_chunk_size = 0x%0x\n", rq_regs->rq_regs_c.min_chunk_size);
+- DTN_INFO("meta_chunk_size = 0x%0x\n", rq_regs->rq_regs_c.meta_chunk_size);
+- DTN_INFO("min_meta_chunk_size = 0x%0x\n", rq_regs->rq_regs_c.min_meta_chunk_size);
+- DTN_INFO("dpte_group_size = 0x%0x\n", rq_regs->rq_regs_c.dpte_group_size);
+- DTN_INFO("mpte_group_size = 0x%0x\n", rq_regs->rq_regs_c.mpte_group_size);
+- DTN_INFO("swath_height = 0x%0x\n", rq_regs->rq_regs_c.swath_height);
+- DTN_INFO("pte_row_height_linear = 0x%0x\n", rq_regs->rq_regs_c.pte_row_height_linear);
+-
+- DTN_INFO("========DLG========\n");
+- DTN_INFO("refcyc_h_blank_end = 0x%0x\n", dlg_regs->refcyc_h_blank_end);
+- DTN_INFO("dlg_vblank_end = 0x%0x\n", dlg_regs->dlg_vblank_end);
+- DTN_INFO("min_dst_y_next_start = 0x%0x\n", dlg_regs->min_dst_y_next_start);
+- DTN_INFO("refcyc_per_htotal = 0x%0x\n", dlg_regs->refcyc_per_htotal);
+- DTN_INFO("refcyc_x_after_scaler = 0x%0x\n", dlg_regs->refcyc_x_after_scaler);
+- DTN_INFO("dst_y_after_scaler = 0x%0x\n", dlg_regs->dst_y_after_scaler);
+- DTN_INFO("dst_y_prefetch = 0x%0x\n", dlg_regs->dst_y_prefetch);
+- DTN_INFO("dst_y_per_vm_vblank = 0x%0x\n", dlg_regs->dst_y_per_vm_vblank);
+- DTN_INFO("dst_y_per_row_vblank = 0x%0x\n", dlg_regs->dst_y_per_row_vblank);
+- DTN_INFO("dst_y_per_vm_flip = 0x%0x\n", dlg_regs->dst_y_per_vm_flip);
+- DTN_INFO("dst_y_per_row_flip = 0x%0x\n", dlg_regs->dst_y_per_row_flip);
+- DTN_INFO("ref_freq_to_pix_freq = 0x%0x\n", dlg_regs->ref_freq_to_pix_freq);
+- DTN_INFO("vratio_prefetch = 0x%0x\n", dlg_regs->vratio_prefetch);
+- DTN_INFO("vratio_prefetch_c = 0x%0x\n", dlg_regs->vratio_prefetch_c);
+- DTN_INFO("refcyc_per_pte_group_vblank_l = 0x%0x\n", dlg_regs->refcyc_per_pte_group_vblank_l);
+- DTN_INFO("refcyc_per_pte_group_vblank_c = 0x%0x\n", dlg_regs->refcyc_per_pte_group_vblank_c);
+- DTN_INFO("refcyc_per_meta_chunk_vblank_l = 0x%0x\n", dlg_regs->refcyc_per_meta_chunk_vblank_l);
+- DTN_INFO("refcyc_per_meta_chunk_vblank_c = 0x%0x\n", dlg_regs->refcyc_per_meta_chunk_vblank_c);
+- DTN_INFO("refcyc_per_pte_group_flip_l = 0x%0x\n", dlg_regs->refcyc_per_pte_group_flip_l);
+- DTN_INFO("refcyc_per_pte_group_flip_c = 0x%0x\n", dlg_regs->refcyc_per_pte_group_flip_c);
+- DTN_INFO("refcyc_per_meta_chunk_flip_l = 0x%0x\n", dlg_regs->refcyc_per_meta_chunk_flip_l);
+- DTN_INFO("refcyc_per_meta_chunk_flip_c = 0x%0x\n", dlg_regs->refcyc_per_meta_chunk_flip_c);
+- DTN_INFO("dst_y_per_pte_row_nom_l = 0x%0x\n", dlg_regs->dst_y_per_pte_row_nom_l);
+- DTN_INFO("dst_y_per_pte_row_nom_c = 0x%0x\n", dlg_regs->dst_y_per_pte_row_nom_c);
+- DTN_INFO("refcyc_per_pte_group_nom_l = 0x%0x\n", dlg_regs->refcyc_per_pte_group_nom_l);
+- DTN_INFO("refcyc_per_pte_group_nom_c = 0x%0x\n", dlg_regs->refcyc_per_pte_group_nom_c);
+- DTN_INFO("dst_y_per_meta_row_nom_l = 0x%0x\n", dlg_regs->dst_y_per_meta_row_nom_l);
+- DTN_INFO("dst_y_per_meta_row_nom_c = 0x%0x\n", dlg_regs->dst_y_per_meta_row_nom_c);
+- DTN_INFO("refcyc_per_meta_chunk_nom_l = 0x%0x\n", dlg_regs->refcyc_per_meta_chunk_nom_l);
+- DTN_INFO("refcyc_per_meta_chunk_nom_c = 0x%0x\n", dlg_regs->refcyc_per_meta_chunk_nom_c);
+- DTN_INFO("refcyc_per_line_delivery_pre_l = 0x%0x\n", dlg_regs->refcyc_per_line_delivery_pre_l);
+- DTN_INFO("refcyc_per_line_delivery_pre_c = 0x%0x\n", dlg_regs->refcyc_per_line_delivery_pre_c);
+- DTN_INFO("refcyc_per_line_delivery_l = 0x%0x\n", dlg_regs->refcyc_per_line_delivery_l);
+- DTN_INFO("refcyc_per_line_delivery_c = 0x%0x\n", dlg_regs->refcyc_per_line_delivery_c);
+- DTN_INFO("chunk_hdl_adjust_cur0 = 0x%0x\n", dlg_regs->chunk_hdl_adjust_cur0);
+- DTN_INFO("dst_y_offset_cur1 = 0x%0x\n", dlg_regs->dst_y_offset_cur1);
+- DTN_INFO("chunk_hdl_adjust_cur1 = 0x%0x\n", dlg_regs->chunk_hdl_adjust_cur1);
+- DTN_INFO("vready_after_vcount0 = 0x%0x\n", dlg_regs->vready_after_vcount0);
+- DTN_INFO("dst_y_delta_drq_limit = 0x%0x\n", dlg_regs->dst_y_delta_drq_limit);
+- DTN_INFO("xfc_reg_transfer_delay = 0x%0x\n", dlg_regs->xfc_reg_transfer_delay);
+- DTN_INFO("xfc_reg_precharge_delay = 0x%0x\n", dlg_regs->xfc_reg_precharge_delay);
+- DTN_INFO("xfc_reg_remote_surface_flip_latency = 0x%0x\n", dlg_regs->xfc_reg_remote_surface_flip_latency);
+-
+- DTN_INFO("========TTU========\n");
+- DTN_INFO("qos_level_low_wm = 0x%0x\n", ttu_regs->qos_level_low_wm);
+- DTN_INFO("qos_level_high_wm = 0x%0x\n", ttu_regs->qos_level_high_wm);
+- DTN_INFO("min_ttu_vblank = 0x%0x\n", ttu_regs->min_ttu_vblank);
+- DTN_INFO("qos_level_flip = 0x%0x\n", ttu_regs->qos_level_flip);
+- DTN_INFO("refcyc_per_req_delivery_pre_l = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_pre_l);
+- DTN_INFO("refcyc_per_req_delivery_l = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_l);
+- DTN_INFO("refcyc_per_req_delivery_pre_c = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_pre_c);
+- DTN_INFO("refcyc_per_req_delivery_c = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_c);
+- DTN_INFO("refcyc_per_req_delivery_cur0 = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_cur0);
+- DTN_INFO("refcyc_per_req_delivery_pre_cur0 = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_pre_cur0);
+- DTN_INFO("refcyc_per_req_delivery_cur1 = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_cur1);
+- DTN_INFO("refcyc_per_req_delivery_pre_cur1 = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_pre_cur1);
+- DTN_INFO("qos_level_fixed_l = 0x%0x\n", ttu_regs->qos_level_fixed_l);
+- DTN_INFO("qos_ramp_disable_l = 0x%0x\n", ttu_regs->qos_ramp_disable_l);
+- DTN_INFO("qos_level_fixed_c = 0x%0x\n", ttu_regs->qos_level_fixed_c);
+- DTN_INFO("qos_ramp_disable_c = 0x%0x\n", ttu_regs->qos_ramp_disable_c);
+- DTN_INFO("qos_level_fixed_cur0 = 0x%0x\n", ttu_regs->qos_level_fixed_cur0);
+- DTN_INFO("qos_ramp_disable_cur0 = 0x%0x\n", ttu_regs->qos_ramp_disable_cur0);
+- DTN_INFO("qos_level_fixed_cur1 = 0x%0x\n", ttu_regs->qos_level_fixed_cur1);
+- DTN_INFO("qos_ramp_disable_cur1 = 0x%0x\n", ttu_regs->qos_ramp_disable_cur1);
+-}
+-
+-void dcn10_log_hw_state(struct dc *dc)
++static void dcn10_log_hubp_states(struct dc *dc)
+ {
+ struct dc_context *dc_ctx = dc->ctx;
+ struct resource_pool *pool = dc->res_pool;
+ int i;
+
+- DTN_INFO_BEGIN();
+-
+- dcn10_log_hubbub_state(dc);
+-
+ DTN_INFO("HUBP: format addr_hi width height"
+ " rot mir sw_mode dcc_en blank_en ttu_dis underflow"
+ " min_ttu_vblank qos_low_wm qos_high_wm\n");
+ for (i = 0; i < pool->pipe_count; i++) {
+ struct hubp *hubp = pool->hubps[i];
+- struct dcn_hubp_state s;
++ struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
+
+- hubp->funcs->hubp_read_state(hubp, &s);
++ hubp->funcs->hubp_read_state(hubp);
+
+ DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh"
+ " %6d %8d %7d %8xh",
+ hubp->inst,
+- s.pixel_format,
+- s.inuse_addr_hi,
+- s.viewport_width,
+- s.viewport_height,
+- s.rotation_angle,
+- s.h_mirror_en,
+- s.sw_mode,
+- s.dcc_en,
+- s.blank_en,
+- s.ttu_disable,
+- s.underflow_status);
+- DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
+- DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
+- DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
++ s->pixel_format,
++ s->inuse_addr_hi,
++ s->viewport_width,
++ s->viewport_height,
++ s->rotation_angle,
++ s->h_mirror_en,
++ s->sw_mode,
++ s->dcc_en,
++ s->blank_en,
++ s->ttu_disable,
++ s->underflow_status);
++ DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
++ DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
++ DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
+ DTN_INFO("\n");
+ }
++
++ DTN_INFO("\n=========RQ========\n");
++ DTN_INFO("HUBP: drq_exp_m prq_exp_m mrq_exp_m crq_exp_m plane1_ba L:chunk_s min_chu_s meta_ch_s"
++ " min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h C:chunk_s min_chu_s meta_ch_s"
++ " min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h\n");
++ for (i = 0; i < pool->pipe_count; i++) {
++ struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
++ struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
++
++ DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
++ i, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
++ rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
++ rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
++ rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
++ rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
++ rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
++ rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
++ rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
++ rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
++ }
++
++ DTN_INFO("========DLG========\n");
++ DTN_INFO("HUBP: rc_hbe dlg_vbe min_d_y_n rc_per_ht rc_x_a_s "
++ " dst_y_a_s dst_y_pf dst_y_vvb dst_y_rvb dst_y_vfl dst_y_rfl rf_pix_fq"
++ " vratio_pf vrat_pf_c rc_pg_vbl rc_pg_vbc rc_mc_vbl rc_mc_vbc rc_pg_fll"
++ " rc_pg_flc rc_mc_fll rc_mc_flc pr_nom_l pr_nom_c rc_pg_nl rc_pg_nc "
++ " mr_nom_l mr_nom_c rc_mc_nl rc_mc_nc rc_ld_pl rc_ld_pc rc_ld_l "
++ " rc_ld_c cha_cur0 ofst_cur1 cha_cur1 vr_af_vc0 ddrq_limt x_rt_dlay"
++ " x_rp_dlay x_rr_sfl\n");
++ for (i = 0; i < pool->pipe_count; i++) {
++ struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
++ struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
++
++ DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
++ "% 8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
++ " %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
++ i, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
++ dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
++ dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
++ dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
++ dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
++ dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
++ dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
++ dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
++ dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
++ dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
++ dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
++ dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
++ dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
++ dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
++ dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
++ dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
++ dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
++ dlg_regs->xfc_reg_remote_surface_flip_latency);
++ }
++
++ DTN_INFO("========TTU========\n");
++ DTN_INFO("HUBP: qos_ll_wm qos_lh_wm mn_ttu_vb qos_l_flp rc_rd_p_l rc_rd_l rc_rd_p_c"
++ " rc_rd_c rc_rd_c0 rc_rd_pc0 rc_rd_c1 rc_rd_pc1 qos_lf_l qos_rds_l"
++ " qos_lf_c qos_rds_c qos_lf_c0 qos_rds_c0 qos_lf_c1 qos_rds_c1\n");
++ for (i = 0; i < pool->pipe_count; i++) {
++ struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
++ struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
++
++ DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
++ i, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
++ ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
++ ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
++ ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
++ ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
++ ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
++ ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
++ }
+ DTN_INFO("\n");
++}
++
++void dcn10_log_hw_state(struct dc *dc)
++{
++ struct dc_context *dc_ctx = dc->ctx;
++ struct resource_pool *pool = dc->res_pool;
++ int i;
++
++ DTN_INFO_BEGIN();
++
++ dcn10_log_hubbub_state(dc);
++
++ dcn10_log_hubp_states(dc);
+
+ DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode"
+ " GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 "
+@@ -340,19 +324,6 @@ void dcn10_log_hw_state(struct dc *dc)
+ }
+ DTN_INFO("\n");
+
+- for (i = 0; i < pool->pipe_count; i++) {
+- struct hubp *hubp = pool->hubps[i];
+- struct dcn_hubp_state s = {0};
+-
+- if (!dc->current_state->res_ctx.pipe_ctx[i].stream)
+- continue;
+-
+- hubp->funcs->hubp_read_state(hubp, &s);
+- DTN_INFO("RQ-DLG-TTU registers for HUBP%d:\n", i);
+- print_rq_dlg_ttu_regs(dc_ctx, &s);
+- DTN_INFO("\n");
+- }
+-
+ DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n"
+ "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
+ dc->current_state->bw.dcn.calc_clk.dcfclk_khz,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+index 3866147..331f8ff 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+@@ -56,26 +56,6 @@ struct hubp {
+ bool power_gated;
+ };
+
+-struct dcn_hubp_state {
+- struct _vcs_dpi_display_dlg_regs_st dlg_attr;
+- struct _vcs_dpi_display_ttu_regs_st ttu_attr;
+- struct _vcs_dpi_display_rq_regs_st rq_regs;
+- uint32_t pixel_format;
+- uint32_t inuse_addr_hi;
+- uint32_t viewport_width;
+- uint32_t viewport_height;
+- uint32_t rotation_angle;
+- uint32_t h_mirror_en;
+- uint32_t sw_mode;
+- uint32_t dcc_en;
+- uint32_t blank_en;
+- uint32_t underflow_status;
+- uint32_t ttu_disable;
+- uint32_t min_ttu_vblank;
+- uint32_t qos_level_low_wm;
+- uint32_t qos_level_high_wm;
+-};
+-
+ struct hubp_funcs {
+ void (*hubp_setup)(
+ struct hubp *hubp,
+@@ -140,7 +120,7 @@ struct hubp_funcs {
+
+ void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);
+ void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);
+- void (*hubp_read_state)(struct hubp *hubp, struct dcn_hubp_state *s);
++ void (*hubp_read_state)(struct hubp *hubp);
+
+ };
+
+--
+2.7.4
+