diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4350-drm-amd-display-add-some-DTN-logs-for-input-and-outp.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4350-drm-amd-display-add-some-DTN-logs-for-input-and-outp.patch | 208 |
1 files changed, 208 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4350-drm-amd-display-add-some-DTN-logs-for-input-and-outp.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4350-drm-amd-display-add-some-DTN-logs-for-input-and-outp.patch new file mode 100644 index 00000000..68b3b737 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4350-drm-amd-display-add-some-DTN-logs-for-input-and-outp.patch @@ -0,0 +1,208 @@ +From e7700a4c9891e43baf82f7f39189cef1f98c2936 Mon Sep 17 00:00:00 2001 +From: Anthony Koo <Anthony.Koo@amd.com> +Date: Fri, 13 Apr 2018 09:40:21 -0400 +Subject: [PATCH 4350/5725] drm/amd/display: add some DTN logs for input and + output tf + +Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> +Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 25 +++++++++++++ + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 27 ++++++++++++++ + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 41 ++++++++++++++++++++++ + drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 16 +++++++++ + 4 files changed, 109 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +index c008a71..8c4d9e5 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +@@ -98,6 +98,30 @@ enum gamut_remap_select { + GAMUT_REMAP_COMB_COEFF + }; + ++void dpp_read_state(struct dpp *dpp_base, ++ struct dcn_dpp_state *s) ++{ ++ struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); ++ ++ REG_GET(CM_IGAM_CONTROL, ++ CM_IGAM_LUT_MODE, &s->igam_lut_mode); ++ REG_GET(CM_IGAM_CONTROL, ++ CM_IGAM_INPUT_FORMAT, &s->igam_input_format); ++ REG_GET(CM_DGAM_CONTROL, ++ CM_DGAM_LUT_MODE, &s->dgam_lut_mode); ++ REG_GET(CM_RGAM_CONTROL, ++ CM_RGAM_LUT_MODE, &s->rgam_lut_mode); ++ REG_GET(CM_GAMUT_REMAP_CONTROL, ++ CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode); ++ ++ s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12); ++ s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14); ++ s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22); ++ s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24); ++ s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32); ++ s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34); ++} ++ + /* Program gamut remap in bypass mode */ + void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp) + { +@@ -450,6 +474,7 @@ void dpp1_dppclk_control( + } + + static const struct dpp_funcs dcn10_dpp_funcs = { ++ .dpp_read_state = dpp_read_state, + .dpp_reset = dpp_reset, + .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, + .dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +index 3fccf99..5944a3b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +@@ -44,6 +44,10 @@ + #define TF_REG_LIST_DCN(id) \ + SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\ + SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\ ++ SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\ ++ SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\ ++ SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\ ++ SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\ + SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\ + SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \ + SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \ +@@ -177,6 +181,14 @@ + TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\ + TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\ + TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\ ++ TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\ ++ TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\ ++ TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\ ++ TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\ ++ TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\ ++ TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\ ++ TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\ ++ TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\ + TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\ + TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\ + TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\ +@@ -524,6 +536,14 @@ + type CM_GAMUT_REMAP_MODE; \ + type CM_GAMUT_REMAP_C11; \ + type CM_GAMUT_REMAP_C12; \ ++ type CM_GAMUT_REMAP_C13; \ ++ type CM_GAMUT_REMAP_C14; \ ++ type CM_GAMUT_REMAP_C21; \ ++ type CM_GAMUT_REMAP_C22; \ ++ type CM_GAMUT_REMAP_C23; \ ++ type CM_GAMUT_REMAP_C24; \ ++ type CM_GAMUT_REMAP_C31; \ ++ type CM_GAMUT_REMAP_C32; \ + type CM_GAMUT_REMAP_C33; \ + type CM_GAMUT_REMAP_C34; \ + type CM_COMA_C11; \ +@@ -1095,6 +1115,10 @@ struct dcn_dpp_mask { + uint32_t RECOUT_SIZE; \ + uint32_t CM_GAMUT_REMAP_CONTROL; \ + uint32_t CM_GAMUT_REMAP_C11_C12; \ ++ uint32_t CM_GAMUT_REMAP_C13_C14; \ ++ uint32_t CM_GAMUT_REMAP_C21_C22; \ ++ uint32_t CM_GAMUT_REMAP_C23_C24; \ ++ uint32_t CM_GAMUT_REMAP_C31_C32; \ + uint32_t CM_GAMUT_REMAP_C33_C34; \ + uint32_t CM_COMA_C11_C12; \ + uint32_t CM_COMA_C33_C34; \ +@@ -1407,6 +1431,9 @@ bool dpp_get_optimal_number_of_taps( + struct scaler_data *scl_data, + const struct scaling_taps *in_taps); + ++void dpp_read_state(struct dpp *dpp_base, ++ struct dcn_dpp_state *s); ++ + void dpp_reset(struct dpp *dpp_base); + + void dpp1_cm_program_regamma_lut( +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 48eaf6a..9be751f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -250,6 +250,47 @@ void dcn10_log_hw_state(struct dc *dc) + } + DTN_INFO("\n"); + ++ DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode" ++ " GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 " ++ "C31 C32 C33 C34\n"); ++ for (i = 0; i < pool->pipe_count; i++) { ++ struct dpp *dpp = pool->dpps[i]; ++ struct dcn_dpp_state s; ++ ++ dpp->funcs->dpp_read_state(dpp, &s); ++ ++ DTN_INFO("[%2d]: %11xh %-11s %-11s %-11s" ++ "%08xh %08xh %08xh %08xh %08xh %08xh %08xh", ++ dpp->inst, ++ s.igam_input_format, ++ (s.igam_lut_mode == 0) ? "BypassFixed" : ++ ((s.igam_lut_mode == 1) ? "BypassFloat" : ++ ((s.igam_lut_mode == 2) ? "RAM" : ++ ((s.igam_lut_mode == 3) ? "RAM" : ++ "Unknown"))), ++ (s.dgam_lut_mode == 0) ? "Bypass" : ++ ((s.dgam_lut_mode == 1) ? "sRGB" : ++ ((s.dgam_lut_mode == 2) ? "Ycc" : ++ ((s.dgam_lut_mode == 3) ? "RAM" : ++ ((s.dgam_lut_mode == 4) ? "RAM" : ++ "Unknown")))), ++ (s.rgam_lut_mode == 0) ? "Bypass" : ++ ((s.rgam_lut_mode == 1) ? "sRGB" : ++ ((s.rgam_lut_mode == 2) ? "Ycc" : ++ ((s.rgam_lut_mode == 3) ? "RAM" : ++ ((s.rgam_lut_mode == 4) ? "RAM" : ++ "Unknown")))), ++ s.gamut_remap_mode, ++ s.gamut_remap_c11_c12, ++ s.gamut_remap_c13_c14, ++ s.gamut_remap_c21_c22, ++ s.gamut_remap_c23_c24, ++ s.gamut_remap_c31_c32, ++ s.gamut_remap_c33_c34); ++ DTN_INFO("\n"); ++ } ++ DTN_INFO("\n"); ++ + DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE\n"); + for (i = 0; i < pool->pipe_count; i++) { + struct mpcc_state s = {0}; +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +index bb7af1b..582458f 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +@@ -44,7 +44,23 @@ struct dpp_grph_csc_adjustment { + enum graphics_gamut_adjust_type gamut_adjust_type; + }; + ++struct dcn_dpp_state { ++ uint32_t igam_lut_mode; ++ uint32_t igam_input_format; ++ uint32_t dgam_lut_mode; ++ uint32_t rgam_lut_mode; ++ uint32_t gamut_remap_mode; ++ uint32_t gamut_remap_c11_c12; ++ uint32_t gamut_remap_c13_c14; ++ uint32_t gamut_remap_c21_c22; ++ uint32_t gamut_remap_c23_c24; ++ uint32_t gamut_remap_c31_c32; ++ uint32_t gamut_remap_c33_c34; ++}; ++ + struct dpp_funcs { ++ void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s); ++ + void (*dpp_reset)(struct dpp *dpp); + + void (*dpp_set_scaler)(struct dpp *dpp, +-- +2.7.4 + |