diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4349-drm-amd-display-add-cursor-TTU-CRQ-related.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4349-drm-amd-display-add-cursor-TTU-CRQ-related.patch | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4349-drm-amd-display-add-cursor-TTU-CRQ-related.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4349-drm-amd-display-add-cursor-TTU-CRQ-related.patch new file mode 100644 index 00000000..a77e7765 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4349-drm-amd-display-add-cursor-TTU-CRQ-related.patch @@ -0,0 +1,69 @@ +From 07adcbd5cf7e8d35032e85ca550babc630ac9dd9 Mon Sep 17 00:00:00 2001 +From: Charlene Liu <charlene.liu@amd.com> +Date: Mon, 16 Apr 2018 15:14:15 -0400 +Subject: [PATCH 4349/5725] drm/amd/display: add cursor TTU CRQ related + +Signed-off-by: Charlene Liu <charlene.liu@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 7 +++++++ + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 10 +++++++++- + 2 files changed, 16 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +index 5806217..759fcd1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +@@ -613,6 +613,13 @@ void hubp1_program_deadline( + REG_SET(DCN_SURF1_TTU_CNTL1, 0, + REFCYC_PER_REQ_DELIVERY_PRE, + ttu_attr->refcyc_per_req_delivery_pre_c); ++ ++ REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, ++ REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, ++ QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, ++ QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); ++ REG_SET(DCN_CUR0_TTU_CNTL1, 0, ++ REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); + } + + static void hubp1_setup( +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +index 920ae3a..02045a8 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +@@ -93,6 +93,8 @@ + SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\ + SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\ + SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\ ++ SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\ ++ SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\ + SRI(HUBP_CLK_CNTL, HUBP, id) + + /* Register address initialization macro for ASICs with VM */ +@@ -203,6 +205,8 @@ + uint32_t DCN_SURF0_TTU_CNTL1; \ + uint32_t DCN_SURF1_TTU_CNTL0; \ + uint32_t DCN_SURF1_TTU_CNTL1; \ ++ uint32_t DCN_CUR0_TTU_CNTL0; \ ++ uint32_t DCN_CUR0_TTU_CNTL1; \ + uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \ + uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \ + uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \ +@@ -368,7 +372,11 @@ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ +- HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh) ++ HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\ ++ HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ ++ HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ ++ HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ ++ HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh) + + #define HUBP_MASK_SH_LIST_DCN10(mask_sh)\ + HUBP_MASK_SH_LIST_DCN(mask_sh),\ +-- +2.7.4 + |