diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4330-drm-amd-powerplay-add-smu75-header-files.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4330-drm-amd-powerplay-add-smu75-header-files.patch | 1676 |
1 files changed, 1676 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4330-drm-amd-powerplay-add-smu75-header-files.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4330-drm-amd-powerplay-add-smu75-header-files.patch new file mode 100644 index 00000000..9fe6946a --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4330-drm-amd-powerplay-add-smu75-header-files.patch @@ -0,0 +1,1676 @@ +From 27db33307a4082558297f1d5ffc5ddfe4b866778 Mon Sep 17 00:00:00 2001 +From: Eric Huang <JinHuiEric.Huang@amd.com> +Date: Thu, 9 Nov 2017 16:29:28 -0500 +Subject: [PATCH 4330/5725] drm/amd/powerplay: add smu75 header files + +Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/inc/smu75.h | 760 ++++++++++++++++++ + drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h | 886 +++++++++++++++++++++ + 2 files changed, 1646 insertions(+) + create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu75.h + create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h + +diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu75.h b/drivers/gpu/drm/amd/powerplay/inc/smu75.h +new file mode 100644 +index 0000000..7715230 +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/inc/smu75.h +@@ -0,0 +1,760 @@ ++/* ++ * Copyright 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifndef SMU75_H ++#define SMU75_H ++ ++#pragma pack(push, 1) ++ ++typedef struct { ++ uint32_t high; ++ uint32_t low; ++} data_64_t; ++ ++typedef struct { ++ data_64_t high; ++ data_64_t low; ++} data_128_t; ++ ++#define SMU__DGPU_ONLY ++ ++#define SMU__NUM_SCLK_DPM_STATE 8 ++#define SMU__NUM_MCLK_DPM_LEVELS 4 ++#define SMU__NUM_LCLK_DPM_LEVELS 8 ++#define SMU__NUM_PCIE_DPM_LEVELS 8 ++ ++#define SMU7_CONTEXT_ID_SMC 1 ++#define SMU7_CONTEXT_ID_VBIOS 2 ++ ++#define SMU75_MAX_LEVELS_VDDC 16 ++#define SMU75_MAX_LEVELS_VDDGFX 16 ++#define SMU75_MAX_LEVELS_VDDCI 8 ++#define SMU75_MAX_LEVELS_MVDD 4 ++ ++#define SMU_MAX_SMIO_LEVELS 4 ++ ++#define SMU75_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE ++#define SMU75_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS ++#define SMU75_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS ++#define SMU75_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS ++#define SMU75_MAX_LEVELS_UVD 8 ++#define SMU75_MAX_LEVELS_VCE 8 ++#define SMU75_MAX_LEVELS_ACP 8 ++#define SMU75_MAX_LEVELS_SAMU 8 ++#define SMU75_MAX_ENTRIES_SMIO 32 ++ ++#define DPM_NO_LIMIT 0 ++#define DPM_NO_UP 1 ++#define DPM_GO_DOWN 2 ++#define DPM_GO_UP 3 ++ ++#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 ++#define SMU7_FIRST_DPM_MEMORY_LEVEL 0 ++ ++#define GPIO_CLAMP_MODE_VRHOT 1 ++#define GPIO_CLAMP_MODE_THERM 2 ++#define GPIO_CLAMP_MODE_DC 4 ++ ++#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 ++#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) ++#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 ++#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) ++#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 ++#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) ++#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 ++#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) ++#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 ++#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) ++#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 ++#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) ++#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 ++#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) ++#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 ++#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) ++#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 ++#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) ++#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 ++#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) ++ ++/* Virtualization Defines */ ++#define CG_XDMA_MASK 0x1 ++#define CG_XDMA_SHIFT 0 ++#define CG_UVD_MASK 0x2 ++#define CG_UVD_SHIFT 1 ++#define CG_VCE_MASK 0x4 ++#define CG_VCE_SHIFT 2 ++#define CG_SAMU_MASK 0x8 ++#define CG_SAMU_SHIFT 3 ++#define CG_GFX_MASK 0x10 ++#define CG_GFX_SHIFT 4 ++#define CG_SDMA_MASK 0x20 ++#define CG_SDMA_SHIFT 5 ++#define CG_HDP_MASK 0x40 ++#define CG_HDP_SHIFT 6 ++#define CG_MC_MASK 0x80 ++#define CG_MC_SHIFT 7 ++#define CG_DRM_MASK 0x100 ++#define CG_DRM_SHIFT 8 ++#define CG_ROM_MASK 0x200 ++#define CG_ROM_SHIFT 9 ++#define CG_BIF_MASK 0x400 ++#define CG_BIF_SHIFT 10 ++ ++#if defined SMU__DGPU_ONLY ++#define SMU75_DTE_ITERATIONS 5 ++#define SMU75_DTE_SOURCES 3 ++#define SMU75_DTE_SINKS 1 ++#define SMU75_NUM_CPU_TES 0 ++#define SMU75_NUM_GPU_TES 1 ++#define SMU75_NUM_NON_TES 2 ++#define SMU75_DTE_FAN_SCALAR_MIN 0x100 ++#define SMU75_DTE_FAN_SCALAR_MAX 0x166 ++#define SMU75_DTE_FAN_TEMP_MAX 93 ++#define SMU75_DTE_FAN_TEMP_MIN 83 ++#endif ++#define SMU75_THERMAL_INPUT_LOOP_COUNT 2 ++#define SMU75_THERMAL_CLAMP_MODE_COUNT 2 ++ ++#define EXP_M1_1 93 ++#define EXP_M2_1 195759 ++#define EXP_B_1 111176531 ++ ++#define EXP_M1_2 67 ++#define EXP_M2_2 153720 ++#define EXP_B_2 94415767 ++ ++#define EXP_M1_3 48 ++#define EXP_M2_3 119796 ++#define EXP_B_3 79195279 ++ ++#define EXP_M1_4 550 ++#define EXP_M2_4 1484190 ++#define EXP_B_4 1051432828 ++ ++#define EXP_M1_5 394 ++#define EXP_M2_5 1143049 ++#define EXP_B_5 864288432 ++ ++struct SMU7_HystController_Data { ++ uint16_t waterfall_up; ++ uint16_t waterfall_down; ++ uint16_t waterfall_limit; ++ uint16_t release_cnt; ++ uint16_t release_limit; ++ uint16_t spare; ++}; ++ ++typedef struct SMU7_HystController_Data SMU7_HystController_Data; ++ ++struct SMU75_PIDController { ++ uint32_t Ki; ++ int32_t LFWindupUpperLim; ++ int32_t LFWindupLowerLim; ++ uint32_t StatePrecision; ++ uint32_t LfPrecision; ++ uint32_t LfOffset; ++ uint32_t MaxState; ++ uint32_t MaxLfFraction; ++ uint32_t StateShift; ++}; ++ ++typedef struct SMU75_PIDController SMU75_PIDController; ++ ++struct SMU7_LocalDpmScoreboard { ++ uint32_t PercentageBusy; ++ ++ int32_t PIDError; ++ int32_t PIDIntegral; ++ int32_t PIDOutput; ++ ++ uint32_t SigmaDeltaAccum; ++ uint32_t SigmaDeltaOutput; ++ uint32_t SigmaDeltaLevel; ++ ++ uint32_t UtilizationSetpoint; ++ ++ uint8_t TdpClampMode; ++ uint8_t TdcClampMode; ++ uint8_t ThermClampMode; ++ uint8_t VoltageBusy; ++ ++ int8_t CurrLevel; ++ int8_t TargLevel; ++ uint8_t LevelChangeInProgress; ++ uint8_t UpHyst; ++ ++ uint8_t DownHyst; ++ uint8_t VoltageDownHyst; ++ uint8_t DpmEnable; ++ uint8_t DpmRunning; ++ ++ uint8_t DpmForce; ++ uint8_t DpmForceLevel; ++ uint8_t DisplayWatermark; ++ uint8_t McArbIndex; ++ ++ uint32_t MinimumPerfSclk; ++ ++ uint8_t AcpiReq; ++ uint8_t AcpiAck; ++ uint8_t GfxClkSlow; ++ uint8_t GpioClampMode; ++ ++ uint8_t EnableModeSwitchRLCNotification; ++ uint8_t EnabledLevelsChange; ++ uint8_t DteClampMode; ++ uint8_t FpsClampMode; ++ ++ uint16_t LevelResidencyCounters [SMU75_MAX_LEVELS_GRAPHICS]; ++ uint16_t LevelSwitchCounters [SMU75_MAX_LEVELS_GRAPHICS]; ++ ++ void (*TargetStateCalculator)(uint8_t); ++ void (*SavedTargetStateCalculator)(uint8_t); ++ ++ uint16_t AutoDpmInterval; ++ uint16_t AutoDpmRange; ++ ++ uint8_t FpsEnabled; ++ uint8_t MaxPerfLevel; ++ uint8_t AllowLowClkInterruptToHost; ++ uint8_t FpsRunning; ++ ++ uint32_t MaxAllowedFrequency; ++ ++ uint32_t FilteredSclkFrequency; ++ uint32_t LastSclkFrequency; ++ uint32_t FilteredSclkFrequencyCnt; ++ ++ uint8_t MinPerfLevel; ++#ifdef SMU__FIRMWARE_SCKS_PRESENT__1 ++ uint8_t ScksClampMode; ++ uint8_t padding[2]; ++#else ++ uint8_t padding[3]; ++#endif ++ ++ uint16_t FpsAlpha; ++ uint16_t DeltaTime; ++ uint32_t CurrentFps; ++ uint32_t FilteredFps; ++ uint32_t FrameCount; ++ uint32_t FrameCountLast; ++ uint16_t FpsTargetScalar; ++ uint16_t FpsWaterfallLimitScalar; ++ uint16_t FpsAlphaScalar; ++ uint16_t spare8; ++ SMU7_HystController_Data HystControllerData; ++}; ++ ++typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; ++ ++#define SMU7_MAX_VOLTAGE_CLIENTS 12 ++ ++typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t); ++ ++#define VDDC_MASK 0x00007FFF ++#define VDDC_SHIFT 0 ++#define VDDCI_MASK 0x3FFF8000 ++#define VDDCI_SHIFT 15 ++#define PHASES_MASK 0xC0000000 ++#define PHASES_SHIFT 30 ++ ++typedef uint32_t SMU_VoltageLevel; ++ ++struct SMU7_VoltageScoreboard { ++ SMU_VoltageLevel TargetVoltage; ++ uint16_t MaxVid; ++ uint8_t HighestVidOffset; ++ uint8_t CurrentVidOffset; ++ ++ uint16_t CurrentVddc; ++ uint16_t CurrentVddci; ++ ++ uint8_t ControllerBusy; ++ uint8_t CurrentVid; ++ uint8_t CurrentVddciVid; ++ uint8_t padding; ++ ++ SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; ++ SMU_VoltageLevel TargetVoltageState; ++ uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; ++ ++ uint8_t padding2; ++ uint8_t padding3; ++ uint8_t ControllerEnable; ++ uint8_t ControllerRunning; ++ uint16_t CurrentStdVoltageHiSidd; ++ uint16_t CurrentStdVoltageLoSidd; ++ uint8_t OverrideVoltage; ++ uint8_t padding4; ++ uint8_t padding5; ++ uint8_t CurrentPhases; ++ ++ VoltageChangeHandler_t ChangeVddc; ++ VoltageChangeHandler_t ChangeVddci; ++ VoltageChangeHandler_t ChangePhase; ++ VoltageChangeHandler_t ChangeMvdd; ++ ++ VoltageChangeHandler_t functionLinks[6]; ++ ++ uint16_t * VddcFollower1; ++ int16_t Driver_OD_RequestedVidOffset1; ++ int16_t Driver_OD_RequestedVidOffset2; ++}; ++ ++typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; ++ ++#define SMU7_MAX_PCIE_LINK_SPEEDS 3 ++ ++struct SMU7_PCIeLinkSpeedScoreboard { ++ uint8_t DpmEnable; ++ uint8_t DpmRunning; ++ uint8_t DpmForce; ++ uint8_t DpmForceLevel; ++ ++ uint8_t CurrentLinkSpeed; ++ uint8_t EnabledLevelsChange; ++ uint16_t AutoDpmInterval; ++ ++ uint16_t AutoDpmRange; ++ uint16_t AutoDpmCount; ++ ++ uint8_t DpmMode; ++ uint8_t AcpiReq; ++ uint8_t AcpiAck; ++ uint8_t CurrentLinkLevel; ++}; ++ ++typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; ++ ++#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 ++#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 ++ ++#define SMU7_SCALE_I 7 ++#define SMU7_SCALE_R 12 ++ ++struct SMU7_PowerScoreboard { ++ uint32_t GpuPower; ++ ++ uint32_t VddcPower; ++ uint32_t VddcVoltage; ++ uint32_t VddcCurrent; ++ ++ uint32_t VddciPower; ++ uint32_t VddciVoltage; ++ uint32_t VddciCurrent; ++ ++ uint32_t RocPower; ++ ++ uint16_t Telemetry_1_slope; ++ uint16_t Telemetry_2_slope; ++ int32_t Telemetry_1_offset; ++ int32_t Telemetry_2_offset; ++ ++ uint8_t MCLK_patch_flag; ++ uint8_t reserved[3]; ++}; ++ ++typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; ++ ++#define SMU7_SCLK_DPM_CONFIG_MASK 0x01 ++#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 ++#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 ++#define SMU7_MCLK_DPM_CONFIG_MASK 0x08 ++#define SMU7_UVD_DPM_CONFIG_MASK 0x10 ++#define SMU7_VCE_DPM_CONFIG_MASK 0x20 ++#define SMU7_ACP_DPM_CONFIG_MASK 0x40 ++#define SMU7_SAMU_DPM_CONFIG_MASK 0x80 ++#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 ++ ++#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 ++#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 ++#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 ++#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 ++#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 ++#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 ++ ++struct SMU75_SoftRegisters { ++ uint32_t RefClockFrequency; ++ uint32_t PmTimerPeriod; ++ uint32_t FeatureEnables; ++#if defined (SMU__DGPU_ONLY) ++ uint32_t PreVBlankGap; ++ uint32_t VBlankTimeout; ++ uint32_t TrainTimeGap; ++ uint32_t MvddSwitchTime; ++ uint32_t LongestAcpiTrainTime; ++ uint32_t AcpiDelay; ++ uint32_t G5TrainTime; ++ uint32_t DelayMpllPwron; ++ uint32_t VoltageChangeTimeout; ++#endif ++ uint32_t HandshakeDisables; ++ ++ uint8_t DisplayPhy1Config; ++ uint8_t DisplayPhy2Config; ++ uint8_t DisplayPhy3Config; ++ uint8_t DisplayPhy4Config; ++ ++ uint8_t DisplayPhy5Config; ++ uint8_t DisplayPhy6Config; ++ uint8_t DisplayPhy7Config; ++ uint8_t DisplayPhy8Config; ++ ++ uint32_t AverageGraphicsActivity; ++ uint32_t AverageMemoryActivity; ++ uint32_t AverageGioActivity; ++ ++ uint8_t SClkDpmEnabledLevels; ++ uint8_t MClkDpmEnabledLevels; ++ uint8_t LClkDpmEnabledLevels; ++ uint8_t PCIeDpmEnabledLevels; ++ ++ uint8_t UVDDpmEnabledLevels; ++ uint8_t SAMUDpmEnabledLevels; ++ uint8_t ACPDpmEnabledLevels; ++ uint8_t VCEDpmEnabledLevels; ++ ++ uint32_t DRAM_LOG_ADDR_H; ++ uint32_t DRAM_LOG_ADDR_L; ++ uint32_t DRAM_LOG_PHY_ADDR_H; ++ uint32_t DRAM_LOG_PHY_ADDR_L; ++ uint32_t DRAM_LOG_BUFF_SIZE; ++ uint32_t UlvEnterCount; ++ uint32_t UlvTime; ++ uint32_t UcodeLoadStatus; ++ uint32_t AllowMvddSwitch; ++ uint8_t Activity_Weight; ++ uint8_t Reserved8[3]; ++}; ++ ++typedef struct SMU75_SoftRegisters SMU75_SoftRegisters; ++ ++struct SMU75_Firmware_Header { ++ uint32_t Digest[5]; ++ uint32_t Version; ++ uint32_t HeaderSize; ++ uint32_t Flags; ++ uint32_t EntryPoint; ++ uint32_t CodeSize; ++ uint32_t ImageSize; ++ ++ uint32_t Rtos; ++ uint32_t SoftRegisters; ++ uint32_t DpmTable; ++ uint32_t FanTable; ++ uint32_t CacConfigTable; ++ uint32_t CacStatusTable; ++ uint32_t mcRegisterTable; ++ uint32_t mcArbDramTimingTable; ++ uint32_t PmFuseTable; ++ uint32_t Globals; ++ uint32_t ClockStretcherTable; ++ uint32_t VftTable; ++ uint32_t Reserved1; ++ uint32_t AvfsCksOff_AvfsGbvTable; ++ uint32_t AvfsCksOff_BtcGbvTable; ++ uint32_t MM_AvfsTable; ++ uint32_t PowerSharingTable; ++ uint32_t AvfsTable; ++ uint32_t AvfsCksOffGbvTable; ++ uint32_t AvfsMeanNSigma; ++ uint32_t AvfsSclkOffsetTable; ++ uint32_t Reserved[12]; ++ uint32_t Signature; ++}; ++ ++typedef struct SMU75_Firmware_Header SMU75_Firmware_Header; ++ ++#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 ++ ++enum DisplayConfig { ++ PowerDown = 1, ++ DP54x4, ++ DP54x2, ++ DP54x1, ++ DP27x4, ++ DP27x2, ++ DP27x1, ++ HDMI297, ++ HDMI162, ++ LVDS, ++ DP324x4, ++ DP324x2, ++ DP324x1 ++}; ++ ++#define MC_BLOCK_COUNT 1 ++#define CPL_BLOCK_COUNT 5 ++#define SE_BLOCK_COUNT 15 ++#define GC_BLOCK_COUNT 24 ++ ++struct SMU7_Local_Cac { ++ uint8_t BlockId; ++ uint8_t SignalId; ++ uint8_t Threshold; ++ uint8_t Padding; ++}; ++ ++typedef struct SMU7_Local_Cac SMU7_Local_Cac; ++ ++struct SMU7_Local_Cac_Table { ++ SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; ++ SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; ++ SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT]; ++ SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT]; ++}; ++ ++typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; ++ ++#pragma pack(pop) ++ ++#define CG_SYS_BITMASK_FIRST_BIT 0 ++#define CG_SYS_BITMASK_LAST_BIT 10 ++#define CG_SYS_BIF_MGLS_SHIFT 0 ++#define CG_SYS_ROM_SHIFT 1 ++#define CG_SYS_MC_MGCG_SHIFT 2 ++#define CG_SYS_MC_MGLS_SHIFT 3 ++#define CG_SYS_SDMA_MGCG_SHIFT 4 ++#define CG_SYS_SDMA_MGLS_SHIFT 5 ++#define CG_SYS_DRM_MGCG_SHIFT 6 ++#define CG_SYS_HDP_MGCG_SHIFT 7 ++#define CG_SYS_HDP_MGLS_SHIFT 8 ++#define CG_SYS_DRM_MGLS_SHIFT 9 ++#define CG_SYS_BIF_MGCG_SHIFT 10 ++ ++#define CG_SYS_BIF_MGLS_MASK 0x1 ++#define CG_SYS_ROM_MASK 0x2 ++#define CG_SYS_MC_MGCG_MASK 0x4 ++#define CG_SYS_MC_MGLS_MASK 0x8 ++#define CG_SYS_SDMA_MGCG_MASK 0x10 ++#define CG_SYS_SDMA_MGLS_MASK 0x20 ++#define CG_SYS_DRM_MGCG_MASK 0x40 ++#define CG_SYS_HDP_MGCG_MASK 0x80 ++#define CG_SYS_HDP_MGLS_MASK 0x100 ++#define CG_SYS_DRM_MGLS_MASK 0x200 ++#define CG_SYS_BIF_MGCG_MASK 0x400 ++ ++#define CG_GFX_BITMASK_FIRST_BIT 16 ++#define CG_GFX_BITMASK_LAST_BIT 24 ++ ++#define CG_GFX_CGCG_SHIFT 16 ++#define CG_GFX_CGLS_SHIFT 17 ++#define CG_CPF_MGCG_SHIFT 18 ++#define CG_RLC_MGCG_SHIFT 19 ++#define CG_GFX_OTHERS_MGCG_SHIFT 20 ++#define CG_GFX_3DCG_SHIFT 21 ++#define CG_GFX_3DLS_SHIFT 22 ++#define CG_GFX_RLC_LS_SHIFT 23 ++#define CG_GFX_CP_LS_SHIFT 24 ++ ++#define CG_GFX_CGCG_MASK 0x00010000 ++#define CG_GFX_CGLS_MASK 0x00020000 ++#define CG_CPF_MGCG_MASK 0x00040000 ++#define CG_RLC_MGCG_MASK 0x00080000 ++#define CG_GFX_OTHERS_MGCG_MASK 0x00100000 ++#define CG_GFX_3DCG_MASK 0x00200000 ++#define CG_GFX_3DLS_MASK 0x00400000 ++#define CG_GFX_RLC_LS_MASK 0x00800000 ++#define CG_GFX_CP_LS_MASK 0x01000000 ++ ++ ++#define VRCONF_VDDC_MASK 0x000000FF ++#define VRCONF_VDDC_SHIFT 0 ++#define VRCONF_VDDGFX_MASK 0x0000FF00 ++#define VRCONF_VDDGFX_SHIFT 8 ++#define VRCONF_VDDCI_MASK 0x00FF0000 ++#define VRCONF_VDDCI_SHIFT 16 ++#define VRCONF_MVDD_MASK 0xFF000000 ++#define VRCONF_MVDD_SHIFT 24 ++ ++#define VR_MERGED_WITH_VDDC 0 ++#define VR_SVI2_PLANE_1 1 ++#define VR_SVI2_PLANE_2 2 ++#define VR_SMIO_PATTERN_1 3 ++#define VR_SMIO_PATTERN_2 4 ++#define VR_STATIC_VOLTAGE 5 ++ ++#define CLOCK_STRETCHER_MAX_ENTRIES 0x4 ++#define CKS_LOOKUPTable_MAX_ENTRIES 0x4 ++ ++#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01 ++#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0 ++#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E ++#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1 ++#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80 ++#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7 ++ ++struct SMU_ClockStretcherDataTableEntry { ++ uint8_t minVID; ++ uint8_t maxVID; ++ ++ uint16_t setting; ++}; ++typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry; ++ ++struct SMU_ClockStretcherDataTable { ++ SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES]; ++}; ++typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable; ++ ++struct SMU_CKS_LOOKUPTableEntry { ++ uint16_t minFreq; ++ uint16_t maxFreq; ++ ++ uint8_t setting; ++ uint8_t padding[3]; ++}; ++typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry; ++ ++struct SMU_CKS_LOOKUPTable { ++ SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES]; ++}; ++typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable; ++ ++struct AgmAvfsData_t { ++ uint16_t avgPsmCount[28]; ++ uint16_t minPsmCount[28]; ++}; ++typedef struct AgmAvfsData_t AgmAvfsData_t; ++ ++enum VFT_COLUMNS { ++ SCLK0, ++ SCLK1, ++ SCLK2, ++ SCLK3, ++ SCLK4, ++ SCLK5, ++ SCLK6, ++ SCLK7, ++ ++ NUM_VFT_COLUMNS ++}; ++enum { ++ SCS_FUSE_T0, ++ SCS_FUSE_T1, ++ NUM_SCS_FUSE_TEMPERATURE ++}; ++enum { ++ SCKS_ON, ++ SCKS_OFF, ++ NUM_SCKS_STATE_TYPES ++}; ++ ++#define VFT_TABLE_DEFINED ++ ++#define TEMP_RANGE_MAXSTEPS 12 ++struct VFT_CELL_t { ++ uint16_t Voltage; ++}; ++ ++typedef struct VFT_CELL_t VFT_CELL_t; ++#ifdef SMU__FIRMWARE_SCKS_PRESENT__1 ++struct SCS_CELL_t { ++ uint16_t PsmCnt[NUM_SCKS_STATE_TYPES]; ++}; ++typedef struct SCS_CELL_t SCS_CELL_t; ++#endif ++ ++struct VFT_TABLE_t { ++ VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS]; ++ uint16_t AvfsGbv [NUM_VFT_COLUMNS]; ++ uint16_t BtcGbv [NUM_VFT_COLUMNS]; ++ int16_t Temperature [TEMP_RANGE_MAXSTEPS]; ++ ++#ifdef SMU__FIRMWARE_SCKS_PRESENT__1 ++ SCS_CELL_t ScksCell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS]; ++#endif ++ ++ uint8_t NumTemperatureSteps; ++ uint8_t padding[3]; ++}; ++typedef struct VFT_TABLE_t VFT_TABLE_t; ++ ++#define BTCGB_VDROOP_TABLE_MAX_ENTRIES 2 ++#define AVFSGB_VDROOP_TABLE_MAX_ENTRIES 2 ++ ++struct GB_VDROOP_TABLE_t { ++ int32_t a0; ++ int32_t a1; ++ int32_t a2; ++ uint32_t spare; ++}; ++typedef struct GB_VDROOP_TABLE_t GB_VDROOP_TABLE_t; ++ ++struct SMU_QuadraticCoeffs { ++ int32_t m1; ++ int32_t b; ++ ++ int16_t m2; ++ uint8_t m1_shift; ++ uint8_t m2_shift; ++}; ++typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs; ++ ++struct AVFS_Margin_t { ++ VFT_CELL_t Cell[NUM_VFT_COLUMNS]; ++}; ++typedef struct AVFS_Margin_t AVFS_Margin_t; ++ ++struct AVFS_CksOff_Gbv_t { ++ VFT_CELL_t Cell[NUM_VFT_COLUMNS]; ++}; ++typedef struct AVFS_CksOff_Gbv_t AVFS_CksOff_Gbv_t; ++ ++struct AVFS_CksOff_AvfsGbv_t { ++ VFT_CELL_t Cell[NUM_VFT_COLUMNS]; ++}; ++typedef struct AVFS_CksOff_AvfsGbv_t AVFS_CksOff_AvfsGbv_t; ++ ++struct AVFS_CksOff_BtcGbv_t { ++ VFT_CELL_t Cell[NUM_VFT_COLUMNS]; ++}; ++typedef struct AVFS_CksOff_BtcGbv_t AVFS_CksOff_BtcGbv_t; ++ ++struct AVFS_meanNsigma_t { ++ uint32_t Aconstant[3]; ++ uint16_t DC_tol_sigma; ++ uint16_t Platform_mean; ++ uint16_t Platform_sigma; ++ uint16_t PSM_Age_CompFactor; ++ uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS]; ++}; ++typedef struct AVFS_meanNsigma_t AVFS_meanNsigma_t; ++ ++struct AVFS_Sclk_Offset_t { ++ uint16_t Sclk_Offset[8]; ++}; ++typedef struct AVFS_Sclk_Offset_t AVFS_Sclk_Offset_t; ++ ++struct Power_Sharing_t { ++ uint32_t EnergyCounter; ++ uint32_t EngeryThreshold; ++ uint64_t AM_SCLK_CNT; ++ uint64_t AM_0_BUSY_CNT; ++}; ++typedef struct Power_Sharing_t Power_Sharing_t; ++ ++ ++#endif ++ ++ +diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h +new file mode 100644 +index 0000000..b64e58a2 +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h +@@ -0,0 +1,886 @@ ++/* ++ * Copyright 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++ ++#ifndef SMU75_DISCRETE_H ++#define SMU75_DISCRETE_H ++ ++#include "smu75.h" ++ ++#pragma pack(push, 1) ++ ++#define NUM_SCLK_RANGE 8 ++ ++#define VCO_3_6 1 ++#define VCO_2_4 3 ++ ++#define POSTDIV_DIV_BY_1 0 ++#define POSTDIV_DIV_BY_2 1 ++#define POSTDIV_DIV_BY_4 2 ++#define POSTDIV_DIV_BY_8 3 ++#define POSTDIV_DIV_BY_16 4 ++ ++struct sclkFcwRange_t { ++ uint8_t vco_setting; /* 1: 3-6GHz, 3: 2-4GHz */ ++ uint8_t postdiv; /* divide by 2^n */ ++ uint16_t fcw_pcc; ++ uint16_t fcw_trans_upper; ++ uint16_t fcw_trans_lower; ++}; ++typedef struct sclkFcwRange_t sclkFcwRange_t; ++ ++struct SMIO_Pattern { ++ uint16_t Voltage; ++ uint8_t Smio; ++ uint8_t padding; ++}; ++ ++typedef struct SMIO_Pattern SMIO_Pattern; ++ ++struct SMIO_Table { ++ SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS]; ++}; ++ ++typedef struct SMIO_Table SMIO_Table; ++ ++struct SMU_SclkSetting { ++ uint32_t SclkFrequency; ++ uint16_t Fcw_int; ++ uint16_t Fcw_frac; ++ uint16_t Pcc_fcw_int; ++ uint8_t PllRange; ++ uint8_t SSc_En; ++ uint16_t Sclk_slew_rate; ++ uint16_t Pcc_up_slew_rate; ++ uint16_t Pcc_down_slew_rate; ++ uint16_t Fcw1_int; ++ uint16_t Fcw1_frac; ++ uint16_t Sclk_ss_slew_rate; ++}; ++typedef struct SMU_SclkSetting SMU_SclkSetting; ++ ++struct SMU75_Discrete_GraphicsLevel { ++ SMU_VoltageLevel MinVoltage; ++ ++ uint8_t pcieDpmLevel; ++ uint8_t DeepSleepDivId; ++ uint16_t ActivityLevel; ++ ++ uint32_t CgSpllFuncCntl3; ++ uint32_t CgSpllFuncCntl4; ++ uint32_t CcPwrDynRm; ++ uint32_t CcPwrDynRm1; ++ ++ uint8_t SclkDid; ++ uint8_t padding; ++ uint8_t EnabledForActivity; ++ uint8_t EnabledForThrottle; ++ uint8_t UpHyst; ++ uint8_t DownHyst; ++ uint8_t VoltageDownHyst; ++ uint8_t PowerThrottle; ++ ++ SMU_SclkSetting SclkSetting; ++ ++ uint8_t ScksStretchThreshVid[NUM_SCKS_STATE_TYPES]; ++ uint16_t Padding; ++}; ++ ++typedef struct SMU75_Discrete_GraphicsLevel SMU75_Discrete_GraphicsLevel; ++ ++struct SMU75_Discrete_ACPILevel { ++ uint32_t Flags; ++ SMU_VoltageLevel MinVoltage; ++ uint32_t SclkFrequency; ++ uint8_t SclkDid; ++ uint8_t DisplayWatermark; ++ uint8_t DeepSleepDivId; ++ uint8_t padding; ++ uint32_t CcPwrDynRm; ++ uint32_t CcPwrDynRm1; ++ ++ SMU_SclkSetting SclkSetting; ++}; ++ ++typedef struct SMU75_Discrete_ACPILevel SMU75_Discrete_ACPILevel; ++ ++struct SMU75_Discrete_Ulv { ++ uint32_t CcPwrDynRm; ++ uint32_t CcPwrDynRm1; ++ uint16_t VddcOffset; ++ uint8_t VddcOffsetVid; ++ uint8_t VddcPhase; ++ uint16_t BifSclkDfs; ++ uint16_t Reserved; ++}; ++ ++typedef struct SMU75_Discrete_Ulv SMU75_Discrete_Ulv; ++ ++struct SMU75_Discrete_MemoryLevel { ++ SMU_VoltageLevel MinVoltage; ++ uint32_t MinMvdd; ++ ++ uint32_t MclkFrequency; ++ ++ uint8_t StutterEnable; ++ uint8_t EnabledForThrottle; ++ uint8_t EnabledForActivity; ++ uint8_t padding_0; ++ ++ uint8_t UpHyst; ++ uint8_t DownHyst; ++ uint8_t VoltageDownHyst; ++ uint8_t padding_1; ++ ++ uint16_t ActivityLevel; ++ uint8_t DisplayWatermark; ++ uint8_t padding_2; ++ ++ uint16_t Fcw_int; ++ uint16_t Fcw_frac; ++ uint8_t Postdiv; ++ uint8_t padding_3[3]; ++}; ++ ++typedef struct SMU75_Discrete_MemoryLevel SMU75_Discrete_MemoryLevel; ++ ++struct SMU75_Discrete_LinkLevel { ++ uint8_t PcieGenSpeed; ++ uint8_t PcieLaneCount; ++ uint8_t EnabledForActivity; ++ uint8_t SPC; ++ uint32_t DownThreshold; ++ uint32_t UpThreshold; ++ uint16_t BifSclkDfs; ++ uint16_t Reserved; ++}; ++ ++typedef struct SMU75_Discrete_LinkLevel SMU75_Discrete_LinkLevel; ++ ++ ++/* MC ARB DRAM Timing registers. */ ++struct SMU75_Discrete_MCArbDramTimingTableEntry { ++ uint32_t McArbDramTiming; ++ uint32_t McArbDramTiming2; ++ uint32_t McArbBurstTime; ++ uint32_t McArbRfshRate; ++ uint32_t McArbMisc3; ++}; ++ ++typedef struct SMU75_Discrete_MCArbDramTimingTableEntry SMU75_Discrete_MCArbDramTimingTableEntry; ++ ++struct SMU75_Discrete_MCArbDramTimingTable { ++ SMU75_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; ++}; ++ ++typedef struct SMU75_Discrete_MCArbDramTimingTable SMU75_Discrete_MCArbDramTimingTable; ++ ++/* UVD VCLK/DCLK state (level) definition. */ ++struct SMU75_Discrete_UvdLevel { ++ uint32_t VclkFrequency; ++ uint32_t DclkFrequency; ++ SMU_VoltageLevel MinVoltage; ++ uint8_t VclkDivider; ++ uint8_t DclkDivider; ++ uint8_t padding[2]; ++}; ++ ++typedef struct SMU75_Discrete_UvdLevel SMU75_Discrete_UvdLevel; ++ ++/* Clocks for other external blocks (VCE, ACP, SAMU). */ ++struct SMU75_Discrete_ExtClkLevel { ++ uint32_t Frequency; ++ SMU_VoltageLevel MinVoltage; ++ uint8_t Divider; ++ uint8_t padding[3]; ++}; ++ ++typedef struct SMU75_Discrete_ExtClkLevel SMU75_Discrete_ExtClkLevel; ++ ++struct SMU75_Discrete_StateInfo { ++ uint32_t SclkFrequency; ++ uint32_t MclkFrequency; ++ uint32_t VclkFrequency; ++ uint32_t DclkFrequency; ++ uint32_t SamclkFrequency; ++ uint32_t AclkFrequency; ++ uint32_t EclkFrequency; ++ uint16_t MvddVoltage; ++ uint16_t padding16; ++ uint8_t DisplayWatermark; ++ uint8_t McArbIndex; ++ uint8_t McRegIndex; ++ uint8_t SeqIndex; ++ uint8_t SclkDid; ++ int8_t SclkIndex; ++ int8_t MclkIndex; ++ uint8_t PCIeGen; ++}; ++ ++typedef struct SMU75_Discrete_StateInfo SMU75_Discrete_StateInfo; ++ ++struct SMU75_Discrete_DpmTable { ++ SMU75_PIDController GraphicsPIDController; ++ SMU75_PIDController MemoryPIDController; ++ SMU75_PIDController LinkPIDController; ++ ++ uint32_t SystemFlags; ++ ++ uint32_t VRConfig; ++ uint32_t SmioMask1; ++ uint32_t SmioMask2; ++ SMIO_Table SmioTable1; ++ SMIO_Table SmioTable2; ++ ++ uint32_t MvddLevelCount; ++ ++ uint8_t BapmVddcVidHiSidd [SMU75_MAX_LEVELS_VDDC]; ++ uint8_t BapmVddcVidLoSidd [SMU75_MAX_LEVELS_VDDC]; ++ uint8_t BapmVddcVidHiSidd2 [SMU75_MAX_LEVELS_VDDC]; ++ ++ uint8_t GraphicsDpmLevelCount; ++ uint8_t MemoryDpmLevelCount; ++ uint8_t LinkLevelCount; ++ uint8_t MasterDeepSleepControl; ++ ++ uint8_t UvdLevelCount; ++ uint8_t VceLevelCount; ++ uint8_t AcpLevelCount; ++ uint8_t SamuLevelCount; ++ ++ uint8_t ThermOutGpio; ++ uint8_t ThermOutPolarity; ++ uint8_t ThermOutMode; ++ uint8_t BootPhases; ++ ++ uint8_t VRHotLevel; ++ uint8_t LdoRefSel; ++ ++ uint8_t Reserved1[2]; ++ ++ uint16_t FanStartTemperature; ++ uint16_t FanStopTemperature; ++ ++ uint16_t MaxVoltage; ++ uint16_t Reserved2; ++ uint32_t Reserved; ++ ++ SMU75_Discrete_GraphicsLevel GraphicsLevel [SMU75_MAX_LEVELS_GRAPHICS]; ++ SMU75_Discrete_MemoryLevel MemoryACPILevel; ++ SMU75_Discrete_MemoryLevel MemoryLevel [SMU75_MAX_LEVELS_MEMORY]; ++ SMU75_Discrete_LinkLevel LinkLevel [SMU75_MAX_LEVELS_LINK]; ++ SMU75_Discrete_ACPILevel ACPILevel; ++ SMU75_Discrete_UvdLevel UvdLevel [SMU75_MAX_LEVELS_UVD]; ++ SMU75_Discrete_ExtClkLevel VceLevel [SMU75_MAX_LEVELS_VCE]; ++ SMU75_Discrete_ExtClkLevel AcpLevel [SMU75_MAX_LEVELS_ACP]; ++ SMU75_Discrete_ExtClkLevel SamuLevel [SMU75_MAX_LEVELS_SAMU]; ++ SMU75_Discrete_Ulv Ulv; ++ ++ uint8_t DisplayWatermark [SMU75_MAX_LEVELS_MEMORY][SMU75_MAX_LEVELS_GRAPHICS]; ++ ++ uint32_t SclkStepSize; ++ uint32_t Smio [SMU75_MAX_ENTRIES_SMIO]; ++ ++ uint8_t UvdBootLevel; ++ uint8_t VceBootLevel; ++ uint8_t AcpBootLevel; ++ uint8_t SamuBootLevel; ++ ++ uint8_t GraphicsBootLevel; ++ uint8_t GraphicsVoltageChangeEnable; ++ uint8_t GraphicsThermThrottleEnable; ++ uint8_t GraphicsInterval; ++ ++ uint8_t VoltageInterval; ++ uint8_t ThermalInterval; ++ uint16_t TemperatureLimitHigh; ++ ++ uint16_t TemperatureLimitLow; ++ uint8_t MemoryBootLevel; ++ uint8_t MemoryVoltageChangeEnable; ++ ++ uint16_t BootMVdd; ++ uint8_t MemoryInterval; ++ uint8_t MemoryThermThrottleEnable; ++ ++ uint16_t VoltageResponseTime; ++ uint16_t PhaseResponseTime; ++ ++ uint8_t PCIeBootLinkLevel; ++ uint8_t PCIeGenInterval; ++ uint8_t DTEInterval; ++ uint8_t DTEMode; ++ ++ uint8_t SVI2Enable; ++ uint8_t VRHotGpio; ++ uint8_t AcDcGpio; ++ uint8_t ThermGpio; ++ ++ uint16_t PPM_PkgPwrLimit; ++ uint16_t PPM_TemperatureLimit; ++ ++ uint16_t DefaultTdp; ++ uint16_t TargetTdp; ++ ++ uint16_t FpsHighThreshold; ++ uint16_t FpsLowThreshold; ++ ++ uint16_t BAPMTI_R [SMU75_DTE_ITERATIONS][SMU75_DTE_SOURCES][SMU75_DTE_SINKS]; ++ uint16_t BAPMTI_RC [SMU75_DTE_ITERATIONS][SMU75_DTE_SOURCES][SMU75_DTE_SINKS]; ++ ++ uint16_t TemperatureLimitEdge; ++ uint16_t TemperatureLimitHotspot; ++ ++ uint16_t BootVddc; ++ uint16_t BootVddci; ++ ++ uint16_t FanGainEdge; ++ uint16_t FanGainHotspot; ++ ++ uint32_t LowSclkInterruptThreshold; ++ uint32_t VddGfxReChkWait; ++ ++ uint8_t ClockStretcherAmount; ++ uint8_t Sclk_CKS_masterEn0_7; ++ uint8_t Sclk_CKS_masterEn8_15; ++ uint8_t DPMFreezeAndForced; ++ ++ uint8_t Sclk_voltageOffset[8]; ++ ++ SMU_ClockStretcherDataTable ClockStretcherDataTable; ++ SMU_CKS_LOOKUPTable CKS_LOOKUPTable; ++ ++ uint32_t CurrSclkPllRange; ++ sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE]; ++ ++ GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES]; ++ SMU_QuadraticCoeffs AVFSGB_FUSE_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES]; ++}; ++ ++typedef struct SMU75_Discrete_DpmTable SMU75_Discrete_DpmTable; ++ ++struct SMU75_Discrete_FanTable { ++ uint16_t FdoMode; ++ int16_t TempMin; ++ int16_t TempMed; ++ int16_t TempMax; ++ int16_t Slope1; ++ int16_t Slope2; ++ int16_t FdoMin; ++ int16_t HystUp; ++ int16_t HystDown; ++ int16_t HystSlope; ++ int16_t TempRespLim; ++ int16_t TempCurr; ++ int16_t SlopeCurr; ++ int16_t PwmCurr; ++ uint32_t RefreshPeriod; ++ int16_t FdoMax; ++ uint8_t TempSrc; ++ int8_t Padding; ++}; ++ ++typedef struct SMU75_Discrete_FanTable SMU75_Discrete_FanTable; ++ ++#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 ++#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) ++ ++ ++ ++struct SMU7_MclkDpmScoreboard { ++ uint32_t PercentageBusy; ++ ++ int32_t PIDError; ++ int32_t PIDIntegral; ++ int32_t PIDOutput; ++ ++ uint32_t SigmaDeltaAccum; ++ uint32_t SigmaDeltaOutput; ++ uint32_t SigmaDeltaLevel; ++ ++ uint32_t UtilizationSetpoint; ++ ++ uint8_t TdpClampMode; ++ uint8_t TdcClampMode; ++ uint8_t ThermClampMode; ++ uint8_t VoltageBusy; ++ ++ int8_t CurrLevel; ++ int8_t TargLevel; ++ uint8_t LevelChangeInProgress; ++ uint8_t UpHyst; ++ ++ uint8_t DownHyst; ++ uint8_t VoltageDownHyst; ++ uint8_t DpmEnable; ++ uint8_t DpmRunning; ++ ++ uint8_t DpmForce; ++ uint8_t DpmForceLevel; ++ uint8_t padding2; ++ uint8_t McArbIndex; ++ ++ uint32_t MinimumPerfMclk; ++ ++ uint8_t AcpiReq; ++ uint8_t AcpiAck; ++ uint8_t MclkSwitchInProgress; ++ uint8_t MclkSwitchCritical; ++ ++ uint8_t IgnoreVBlank; ++ uint8_t TargetMclkIndex; ++ uint8_t TargetMvddIndex; ++ uint8_t MclkSwitchResult; ++ ++ uint16_t VbiFailureCount; ++ uint8_t VbiWaitCounter; ++ uint8_t EnabledLevelsChange; ++ ++ uint16_t LevelResidencyCounters [SMU75_MAX_LEVELS_MEMORY]; ++ uint16_t LevelSwitchCounters [SMU75_MAX_LEVELS_MEMORY]; ++ ++ void (*TargetStateCalculator)(uint8_t); ++ void (*SavedTargetStateCalculator)(uint8_t); ++ ++ uint16_t AutoDpmInterval; ++ uint16_t AutoDpmRange; ++ ++ uint16_t VbiTimeoutCount; ++ uint16_t MclkSwitchingTime; ++ ++ uint8_t fastSwitch; ++ uint8_t Save_PIC_VDDGFX_EXIT; ++ uint8_t Save_PIC_VDDGFX_ENTER; ++ uint8_t VbiTimeout; ++ ++ uint32_t HbmTempRegBackup; ++}; ++ ++typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard; ++ ++struct SMU7_UlvScoreboard { ++ uint8_t EnterUlv; ++ uint8_t ExitUlv; ++ uint8_t UlvActive; ++ uint8_t WaitingForUlv; ++ uint8_t UlvEnable; ++ uint8_t UlvRunning; ++ uint8_t UlvMasterEnable; ++ uint8_t padding; ++ uint32_t UlvAbortedCount; ++ uint32_t UlvTimeStamp; ++}; ++ ++typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard; ++ ++struct VddgfxSavedRegisters { ++ uint32_t GPU_DBG[3]; ++ uint32_t MEC_BaseAddress_Hi; ++ uint32_t MEC_BaseAddress_Lo; ++ uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; ++ uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; ++ uint32_t CP_INT_CNTL; ++}; ++ ++typedef struct VddgfxSavedRegisters VddgfxSavedRegisters; ++ ++struct SMU7_VddGfxScoreboard { ++ uint8_t VddGfxEnable; ++ uint8_t VddGfxActive; ++ uint8_t VPUResetOccured; ++ uint8_t padding; ++ ++ uint32_t VddGfxEnteredCount; ++ uint32_t VddGfxAbortedCount; ++ ++ uint32_t VddGfxVid; ++ ++ VddgfxSavedRegisters SavedRegisters; ++}; ++ ++typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard; ++ ++struct SMU7_TdcLimitScoreboard { ++ uint8_t Enable; ++ uint8_t Running; ++ uint16_t Alpha; ++ uint32_t FilteredIddc; ++ uint32_t IddcLimit; ++ uint32_t IddcHyst; ++ SMU7_HystController_Data HystControllerData; ++}; ++ ++typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard; ++ ++struct SMU7_PkgPwrLimitScoreboard { ++ uint8_t Enable; ++ uint8_t Running; ++ uint16_t Alpha; ++ uint32_t FilteredPkgPwr; ++ uint32_t Limit; ++ uint32_t Hyst; ++ uint32_t LimitFromDriver; ++ uint8_t PowerSharingEnabled; ++ uint8_t PowerSharingCounter; ++ uint8_t PowerSharingINTEnabled; ++ uint8_t GFXActivityCounterEnabled; ++ uint32_t EnergyCount; ++ uint32_t PSACTCount; ++ uint8_t RollOverRequired; ++ uint8_t RollOverCount; ++ uint8_t padding[2]; ++ SMU7_HystController_Data HystControllerData; ++}; ++ ++typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard; ++ ++struct SMU7_BapmScoreboard { ++ uint32_t source_powers[SMU75_DTE_SOURCES]; ++ uint32_t source_powers_last[SMU75_DTE_SOURCES]; ++ int32_t entity_temperatures[SMU75_NUM_GPU_TES]; ++ int32_t initial_entity_temperatures[SMU75_NUM_GPU_TES]; ++ int32_t Limit; ++ int32_t Hyst; ++ int32_t therm_influence_coeff_table[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS * 2]; ++ int32_t therm_node_table[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS]; ++ uint16_t ConfigTDPPowerScalar; ++ uint16_t FanSpeedPowerScalar; ++ uint16_t OverDrivePowerScalar; ++ uint16_t OverDriveLimitScalar; ++ uint16_t FinalPowerScalar; ++ uint8_t VariantID; ++ uint8_t spare997; ++ ++ SMU7_HystController_Data HystControllerData; ++ ++ int32_t temperature_gradient_slope; ++ int32_t temperature_gradient; ++ uint32_t measured_temperature; ++}; ++ ++ ++typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard; ++ ++struct SMU7_AcpiScoreboard { ++ uint32_t SavedInterruptMask[2]; ++ uint8_t LastACPIRequest; ++ uint8_t CgBifResp; ++ uint8_t RequestType; ++ uint8_t Padding; ++ SMU75_Discrete_ACPILevel D0Level; ++}; ++ ++typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; ++ ++struct SMU75_Discrete_PmFuses { ++ uint8_t BapmVddCVidHiSidd[8]; ++ ++ uint8_t BapmVddCVidLoSidd[8]; ++ ++ uint8_t VddCVid[8]; ++ ++ uint8_t SviLoadLineEn; ++ uint8_t SviLoadLineVddC; ++ uint8_t SviLoadLineTrimVddC; ++ uint8_t SviLoadLineOffsetVddC; ++ ++ uint16_t TDC_VDDC_PkgLimit; ++ uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; ++ uint8_t TDC_MAWt; ++ ++ uint8_t TdcWaterfallCtl; ++ uint8_t LPMLTemperatureMin; ++ uint8_t LPMLTemperatureMax; ++ uint8_t Reserved; ++ ++ uint8_t LPMLTemperatureScaler[16]; ++ ++ int16_t FuzzyFan_ErrorSetDelta; ++ int16_t FuzzyFan_ErrorRateSetDelta; ++ int16_t FuzzyFan_PwmSetDelta; ++ uint16_t Reserved6; ++ ++ uint8_t GnbLPML[16]; ++ ++ uint8_t GnbLPMLMaxVid; ++ uint8_t GnbLPMLMinVid; ++ uint8_t Reserved1[2]; ++ ++ uint16_t BapmVddCBaseLeakageHiSidd; ++ uint16_t BapmVddCBaseLeakageLoSidd; ++ ++ uint16_t VFT_Temp[3]; ++ uint8_t Version; ++ uint8_t padding; ++ ++ SMU_QuadraticCoeffs VFT_ATE[3]; ++ ++ SMU_QuadraticCoeffs AVFS_GB; ++ SMU_QuadraticCoeffs ATE_ACBTC_GB; ++ ++ SMU_QuadraticCoeffs P2V; ++ ++ uint32_t PsmCharzFreq; ++ ++ uint16_t InversionVoltage; ++ uint16_t PsmCharzTemp; ++ ++ uint32_t EnabledAvfsModules; ++ ++ SMU_QuadraticCoeffs BtcGbv_CksOff; ++}; ++ ++typedef struct SMU75_Discrete_PmFuses SMU75_Discrete_PmFuses; ++ ++struct SMU7_Discrete_Log_Header_Table { ++ uint32_t version; ++ uint32_t asic_id; ++ uint16_t flags; ++ uint16_t entry_size; ++ uint32_t total_size; ++ uint32_t num_of_entries; ++ uint8_t type; ++ uint8_t mode; ++ uint8_t filler_0[2]; ++ uint32_t filler_1[2]; ++}; ++ ++typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table; ++ ++struct SMU7_Discrete_Log_Cntl { ++ uint8_t Enabled; ++ uint8_t Type; ++ uint8_t padding[2]; ++ uint32_t BufferSize; ++ uint32_t SamplesLogged; ++ uint32_t SampleSize; ++ uint32_t AddrL; ++ uint32_t AddrH; ++}; ++ ++typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl; ++ ++#if defined SMU__DGPU_ONLY ++#define CAC_ACC_NW_NUM_OF_SIGNALS 87 ++#endif ++ ++ ++struct SMU7_Discrete_Cac_Collection_Table { ++ uint32_t temperature; ++ uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; ++}; ++ ++typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table; ++ ++struct SMU7_Discrete_Cac_Verification_Table { ++ uint32_t VddcTotalPower; ++ uint32_t VddcLeakagePower; ++ uint32_t VddcConstantPower; ++ uint32_t VddcGfxDynamicPower; ++ uint32_t VddcUvdDynamicPower; ++ uint32_t VddcVceDynamicPower; ++ uint32_t VddcAcpDynamicPower; ++ uint32_t VddcPcieDynamicPower; ++ uint32_t VddcDceDynamicPower; ++ uint32_t VddcCurrent; ++ uint32_t VddcVoltage; ++ uint32_t VddciTotalPower; ++ uint32_t VddciLeakagePower; ++ uint32_t VddciConstantPower; ++ uint32_t VddciDynamicPower; ++ uint32_t Vddr1TotalPower; ++ uint32_t Vddr1LeakagePower; ++ uint32_t Vddr1ConstantPower; ++ uint32_t Vddr1DynamicPower; ++ uint32_t spare[4]; ++ uint32_t temperature; ++}; ++ ++typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table; ++ ++struct SMU7_Discrete_Pm_Status_Table { ++ int32_t T_meas_max[SMU75_THERMAL_INPUT_LOOP_COUNT]; ++ int32_t T_meas_acc[SMU75_THERMAL_INPUT_LOOP_COUNT]; ++ ++ uint32_t I_calc_max; ++ uint32_t I_calc_acc; ++ uint32_t P_meas_acc; ++ uint32_t V_meas_load_acc; ++ uint32_t I_meas_acc; ++ uint32_t P_meas_acc_vddci; ++ uint32_t V_meas_load_acc_vddci; ++ uint32_t I_meas_acc_vddci; ++ ++ uint16_t Sclk_dpm_residency[8]; ++ uint16_t Uvd_dpm_residency[8]; ++ uint16_t Vce_dpm_residency[8]; ++ uint16_t Mclk_dpm_residency[4]; ++ ++ uint32_t P_roc_acc; ++ uint32_t PkgPwr_max; ++ uint32_t PkgPwr_acc; ++ uint32_t MclkSwitchingTime_max; ++ uint32_t MclkSwitchingTime_acc; ++ uint32_t FanPwm_acc; ++ uint32_t FanRpm_acc; ++ uint32_t Gfx_busy_acc; ++ uint32_t Mc_busy_acc; ++ uint32_t Fps_acc; ++ ++ uint32_t AccCnt; ++}; ++ ++typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table; ++ ++struct SMU7_Discrete_AutoWattMan_Status_Table { ++ int32_t T_meas_acc[SMU75_THERMAL_INPUT_LOOP_COUNT]; ++ uint16_t Sclk_dpm_residency[8]; ++ uint16_t Mclk_dpm_residency[4]; ++ uint32_t TgpPwr_acc; ++ uint32_t Gfx_busy_acc; ++ uint32_t Mc_busy_acc; ++ uint32_t AccCnt; ++}; ++ ++typedef struct SMU7_Discrete_AutoWattMan_Status_Table SMU7_Discrete_AutoWattMan_Status_Table; ++ ++#define SMU7_MAX_GFX_CU_COUNT 24 ++#define SMU7_MIN_GFX_CU_COUNT 8 ++#define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_SHIFT 0 ++#define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_MASK (0xFFFF << SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_SHIFT) ++#define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_SHIFT 16 ++#define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_MASK (0xFFFF << SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_SHIFT) ++ ++struct SMU7_GfxCuPgScoreboard { ++ uint8_t Enabled; ++ uint8_t WaterfallUp; ++ uint8_t WaterfallDown; ++ uint8_t WaterfallLimit; ++ uint8_t CurrMaxCu; ++ uint8_t TargMaxCu; ++ uint8_t ClampMode; ++ uint8_t Active; ++ uint8_t MaxSupportedCu; ++ uint8_t MinSupportedCu; ++ uint8_t PendingGfxCuHostInterrupt; ++ uint8_t LastFilteredMaxCuInteger; ++ uint16_t FilteredMaxCu; ++ uint16_t FilteredMaxCuAlpha; ++ uint16_t FilterResetCount; ++ uint16_t FilterResetCountLimit; ++ uint8_t ForceCu; ++ uint8_t ForceCuCount; ++ uint8_t AcModeMaxCu; ++ uint8_t DcModeMaxCu; ++}; ++ ++typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard; ++ ++#define SMU7_SCLK_CAC 0x561 ++#define SMU7_MCLK_CAC 0xF9 ++#define SMU7_VCLK_CAC 0x2DE ++#define SMU7_DCLK_CAC 0x2DE ++#define SMU7_ECLK_CAC 0x25E ++#define SMU7_ACLK_CAC 0x25E ++#define SMU7_SAMCLK_CAC 0x25E ++#define SMU7_DISPCLK_CAC 0x100 ++#define SMU7_CAC_CONSTANT 0x2EE3430 ++#define SMU7_CAC_CONSTANT_SHIFT 18 ++ ++#define SMU7_VDDCI_MCLK_CONST 1765 ++#define SMU7_VDDCI_MCLK_CONST_SHIFT 16 ++#define SMU7_VDDCI_VDDCI_CONST 50958 ++#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14 ++#define SMU7_VDDCI_CONST 11781 ++#define SMU7_VDDCI_STROBE_PWR 1331 ++ ++#define SMU7_VDDR1_CONST 693 ++#define SMU7_VDDR1_CAC_WEIGHT 20 ++#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19 ++#define SMU7_VDDR1_STROBE_PWR 512 ++ ++#define SMU7_AREA_COEFF_UVD 0xA78 ++#define SMU7_AREA_COEFF_VCE 0x190A ++#define SMU7_AREA_COEFF_ACP 0x22D1 ++#define SMU7_AREA_COEFF_SAMU 0x534 ++ ++#define SMU7_THERM_OUT_MODE_DISABLE 0x0 ++#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 ++#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 ++ ++#define SQ_Enable_MASK 0x1 ++#define SQ_IR_MASK 0x2 ++#define SQ_PCC_MASK 0x4 ++#define SQ_EDC_MASK 0x8 ++ ++#define TCP_Enable_MASK 0x100 ++#define TCP_IR_MASK 0x200 ++#define TCP_PCC_MASK 0x400 ++#define TCP_EDC_MASK 0x800 ++ ++#define TD_Enable_MASK 0x10000 ++#define TD_IR_MASK 0x20000 ++#define TD_PCC_MASK 0x40000 ++#define TD_EDC_MASK 0x80000 ++ ++#define DB_Enable_MASK 0x1000000 ++#define DB_IR_MASK 0x2000000 ++#define DB_PCC_MASK 0x4000000 ++#define DB_EDC_MASK 0x8000000 ++ ++#define SQ_Enable_SHIFT 0 ++#define SQ_IR_SHIFT 1 ++#define SQ_PCC_SHIFT 2 ++#define SQ_EDC_SHIFT 3 ++ ++#define TCP_Enable_SHIFT 8 ++#define TCP_IR_SHIFT 9 ++#define TCP_PCC_SHIFT 10 ++#define TCP_EDC_SHIFT 11 ++ ++#define TD_Enable_SHIFT 16 ++#define TD_IR_SHIFT 17 ++#define TD_PCC_SHIFT 18 ++#define TD_EDC_SHIFT 19 ++ ++#define DB_Enable_SHIFT 24 ++#define DB_IR_SHIFT 25 ++#define DB_PCC_SHIFT 26 ++#define DB_EDC_SHIFT 27 ++ ++#define PMFUSES_AVFSSIZE 104 ++ ++#define BTCGB0_Vdroop_Enable_MASK 0x1 ++#define BTCGB1_Vdroop_Enable_MASK 0x2 ++#define AVFSGB0_Vdroop_Enable_MASK 0x4 ++#define AVFSGB1_Vdroop_Enable_MASK 0x8 ++ ++#define BTCGB0_Vdroop_Enable_SHIFT 0 ++#define BTCGB1_Vdroop_Enable_SHIFT 1 ++#define AVFSGB0_Vdroop_Enable_SHIFT 2 ++#define AVFSGB1_Vdroop_Enable_SHIFT 3 ++ ++#pragma pack(pop) ++ ++ ++#endif ++ +-- +2.7.4 + |