diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4276-drm-amdkfd-Fix-typos-in-trap-handler-comments.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4276-drm-amdkfd-Fix-typos-in-trap-handler-comments.patch | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4276-drm-amdkfd-Fix-typos-in-trap-handler-comments.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4276-drm-amdkfd-Fix-typos-in-trap-handler-comments.patch new file mode 100644 index 00000000..ac468ff9 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4276-drm-amdkfd-Fix-typos-in-trap-handler-comments.patch @@ -0,0 +1,85 @@ +From d4b9431a6b77d4a141306c4a20371d20766150a1 Mon Sep 17 00:00:00 2001 +From: Felix Kuehling <Felix.Kuehling@amd.com> +Date: Tue, 17 Apr 2018 18:30:24 -0400 +Subject: [PATCH 4276/5725] drm/amdkfd: Fix typos in trap handler comments + +Fixed for upstreaming to avoid checkpatch warnings. + +Change-Id: Id0e78f1be11c3ee03b2d99bcb9c77cf1221c77fa +Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> +--- + drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm | 8 ++++---- + drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 8 ++++---- + 2 files changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm +index 6302402..a2a04bb 100644 +--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm ++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm +@@ -77,7 +77,7 @@ var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_D + /*************************************************************************/ + /* control on how to run the shader */ + /*************************************************************************/ +-//any hack that needs to be made to run this code in EMU (either becasue various EMU code are not ready or no compute save & restore in EMU run) ++//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run) + var EMU_RUN_HACK = 0 + var EMU_RUN_HACK_RESTORE_NORMAL = 0 + var EMU_RUN_HACK_SAVE_NORMAL_EXIT = 0 +@@ -91,9 +91,9 @@ var WG_BASE_ADDR_HI = 0x0 + var WAVE_SPACE = 0x5000 //memory size that each wave occupies in workgroup state mem + var CTX_SAVE_CONTROL = 0x0 + var CTX_RESTORE_CONTROL = CTX_SAVE_CONTROL +-var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either becasue various RTL code are not ready or no compute save & restore in RTL run) ++var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run) + var SGPR_SAVE_USE_SQC = 1 //use SQC D$ to do the write +-var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //becasue TC EMU curently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes ++var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes + var SWIZZLE_EN = 0 //whether we use swizzled buffer addressing + + /**************************************************************************/ +@@ -1055,7 +1055,7 @@ end + s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 + s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu + +- s_barrier //barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG //FIXME not performance-optimal at this time ++ s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time + + if G8SR_DEBUG_TIMESTAMP + s_memrealtime s_g8sr_ts_restore_d +diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +index fc62fb8..998be96 100644 +--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm ++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +@@ -77,7 +77,7 @@ var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_D + /*************************************************************************/ + /* control on how to run the shader */ + /*************************************************************************/ +-//any hack that needs to be made to run this code in EMU (either becasue various EMU code are not ready or no compute save & restore in EMU run) ++//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run) + var EMU_RUN_HACK = 0 + var EMU_RUN_HACK_RESTORE_NORMAL = 0 + var EMU_RUN_HACK_SAVE_NORMAL_EXIT = 0 +@@ -89,9 +89,9 @@ var WG_BASE_ADDR_HI = 0x0 + var WAVE_SPACE = 0x5000 //memory size that each wave occupies in workgroup state mem + var CTX_SAVE_CONTROL = 0x0 + var CTX_RESTORE_CONTROL = CTX_SAVE_CONTROL +-var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either becasue various RTL code are not ready or no compute save & restore in RTL run) ++var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run) + var SGPR_SAVE_USE_SQC = 1 //use SQC D$ to do the write +-var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //becasue TC EMU curently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes ++var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes + var SWIZZLE_EN = 0 //whether we use swizzled buffer addressing + var ACK_SQC_STORE = 1 //workaround for suspected SQC store bug causing incorrect stores under concurrency + +@@ -1122,7 +1122,7 @@ end + s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 + s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu + +- s_barrier //barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG //FIXME not performance-optimal at this time ++ s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time + + if G8SR_DEBUG_TIMESTAMP + s_memrealtime s_g8sr_ts_restore_d +-- +2.7.4 + |