From 161a61b8f0a1a1cde650e4bc3629249c4029496e Mon Sep 17 00:00:00 2001 From: Weixing Shi Date: Mon, 12 Apr 2010 14:59:38 +0800 Subject: [PATCH] 4kc cache tlb hazard: tlbp cache coherency Add a no-op before tlbp, to avoid DMA cache coherency issues that cause data loss seen on unmount. Signed-off-by: Weixing Shi Signed-off-by: James Perkins --- arch/mips/mm/tlbex.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 97c87027c17f..bc291fe7f44a 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -485,6 +485,7 @@ static void __maybe_unused build_tlb_probe_entry(u32 **p) case CPU_R4700: case CPU_R5000: case CPU_NEVADA: + case CPU_4KC: uasm_i_nop(p); uasm_i_tlbp(p); break; @@ -539,6 +540,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_R4600: case CPU_R4700: + case CPU_4KC: uasm_i_nop(p); tlbw(p); uasm_i_nop(p); @@ -564,7 +566,6 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_R12000: case CPU_R14000: case CPU_R16000: - case CPU_4KC: case CPU_4KEC: case CPU_M14KC: case CPU_M14KEC: -- 2.1.0