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Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
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As part of the merge of the code bases, changes were introduced that
changed the way the cortexr5 was defined. To sync this between the
baremetal compilation and the baremetal toolchain compilation we
create a new armrm tune file, define a new tune feature of 'armrm',
define 'armrm' as a new machine override based on the feature 'armrm',
and move the cortexr5 tuning to a common file.
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
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Baremetal toolchain machines are specific to creating a very specific Xilinx
multilib toolchain configuration. These are not expected to be functional
MACHINE parameters for anything except SDK building.
The expected usage is:
MACHINE=<value> DISTRO=xilinx-standalone bitbake meta-toolchain
Add aarch32-tc
Multilibs:
base: (none)
arm/v5te/softfp: -marm -march=armv5te+fp -mfloat-abi=softfp
arm/v5te/hard: -marm -march=armv5te+fp -mfloat-abi=hard
thumb/nofp: -mthumb -mfloat-abi=soft
thumb/v7/nofp: -mthumb -march=armv7 -mfloat-abi=soft
thumb/v7+fp/softfp: -mthumb -march=armv7+fp -mfloat-abi=softfp
thumb/v7+fp/hard: -mthumb -march=armv7+fp -mfloat-abi=hard
thumb/v7-a/nofp: -mthumb -march=armv7-a -mfloat-abi=soft
thumb/v7-a+fp/softfp: -mthumb -march=armv7-a+fp -mfloat-abi=softfp
thumb/v7-a+fp/hard: -mthumb -march=armv7-a+fp -mfloat-abi=hard
thumb/v7-a+simd/softfp: -mthumb -march=armv7-a+simd -mfloat-abi=softfp
thumb/v7-a+simd/hard: -mthumb -march=armv7-a+simd -mfloat-abi=hard
thumb/v7ve+simd/softfp: -mthumb -march=armv7ve+simd -mfloat-abi=softfp
thumb/v7ve+simd/hard: -mthumb -march=armv7ve+simd -mfloat-abi=hard
thumb/v8-a/nofp: -mthumb -march=armv8-a -mfloat-abi=soft
thumb/v8-a+simd/softfp: -mthumb -march=armv8-a+simd -mfloat-abi=softfp
thumb/v8-a+simd/hard: -mthumb -march=armv8-a+simd -mfloat-abi=hard
Add aarch64-tc
Multilibs:
Base: (none)
ilp32: -mabi=ilp32
- ilp32 requires a custom machine dict
- Add xlnx-standalone.bbclass
- Enable with PACKAGEQA_EXTRA_MACHDEFFUNCS
Add arm-rm-tc
Multilibs:
Base: (none)
arm/v5te/softfp: -marm -march=armv5te+fp -mfloat-abi=softfp
arm/v5te/hard: -marm -march=armv5te+fp -mfloat-abi=hard
thumb/nofp: -mthumb -mfloat-abi=soft
thumb/v7/nofp: -mthumb -march=armv7 -mfloat-abi=soft
thumb/v7+fp/softfp: -mthumb -march=armv7+fp -mfloat-abi=softfp
thumb/v7+fp/hard: -mthumb -march=armv7+fp -mfloat-abi=hard
thumb/v6-m/nofp: -mthumb -march=armv6s-m -mfloat-abi=soft
thumb/v7-m/nofp: -mthumb -march=armv7-m -mfloat-abi=soft
thumb/v7e-m/nofp: -mthumb -march=armv7e-m -mfloat-abi=soft
thumb/v7e-m+fp/softfp: -mthumb -march=armv7e-m+fp -mfloat-abi=softfp
thumb/v7e-m+fp/hard: -mthumb -march=armv7e-m+fp -mfloat-abi=hard
thumb/v7e-m+dp/softfp: -mthumb -march=armv7e-m+fp.dp -mfloat-abi=softfp
thumb/v7e-m+dp/hard: -mthumb -march=armv7e-m+fp.dp -mfloat-abi=hard
thumb/v8-m.base/nofp: -mthumb -march=armv8-m.base -mfloat-abi=soft
thumb/v8-m.main/nofp: -mthumb -march=armv8-m.main -mfloat-abi=soft
thumb/v8-m.main+fp/softfp: -mthumb -march=armv8-m.main+fp -mfloat-abi=softfp
thumb/v8-m.main+fp/hard: -mthumb -march=armv8-m.main+fp -mfloat-abi=hard
thumb/v8-m.main+dp/softfp: -mthumb -march=armv8-m.main+fp.dp -mfloat-abi=softfp
thumb/v8-m.main+dp/hard: -mthumb -march=armv8-m.main+fp.dp -mfloat-abi=hard
Add microblaze-tc
Multilibs:
base: (none)
bs: -mxl-barrel-shift
le: -mlittle-endian
m: -mno-xl-soft-mul
m/mh: -mno-xl-soft-mul -mxl-multiply-high
le/m: -mlittle-endian -mno-xl-soft-mul
le/m/mh: -mlittle-endian -mno-xl-soft-mul -mxl-multiply-high
bs/le: -mxl-barrel-shift -mlittle-endian
bs/m: -mxl-barrel-shift -mno-xl-soft-mul
bs/m/mh: -mxl-barrel-shift -mno-xl-soft-mul -mxl-multiply-high
bs/le/m: -mxl-barrel-shift -mlittle-endian -mno-xl-soft-mul
bs/le/m/mh: -mxl-barrel-shift -mlittle-endian -mno-xl-soft-mul -mxl-multiply-high
m64/le: -m64 -mlittle-endian
m64/le/m: -m64 -mlittle-endian -mno-xl-soft-mul
m64/le/m/mh: -m64 -mlittle-endian -mno-xl-soft-mul -mxl-multiply-high
m64/bs/le: -m64 -mxl-barrel-shift -mlittle-endian
m64/bs/le/m: -m64 -mxl-barrel-shift -mlittle-endian -mno-xl-soft-mul
m64/bs/le/m/mh: -m64 -mxl-barrel-shift -mlittle-endian -mno-xl-soft-mul -mxl-multiply-high
- 64-bit MicroBlaze requires a custom machine dict
- Add xlnx-standalone.bbclass
- Enable with PACKAGEQA_EXTRA_MACHDEFFUNCS
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
Please enter the commit message for your changes. Lines starting
with '#' will be ignored, and an empty message aborts the commit.
Date: Thu Jan 30 12:17:59 2020 -0800
On branch multilib-baremetal
Your branch is ahead of 'xilinx/master-next' by 2 commits.
(use "git push" to publish your local commits)
Changes to be committed:
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backend"""
This reverts commit 55aa631780a5d804324bbb348b5df9b5d0c1f934.
Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
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Using the optimized tune file (tune-cortexa72-cortexa53.inc) instead of
armv8a tune for versal and zynqmp.
Also changing DEFAULTTUNE from aarch64 to cortexa72-cortexa53 as
otherwise it was taking aarch64, the first declared default
Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
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mali backend""
This reverts commit 7719c87e2574a6ed2b15b99c43ecbee5cebb3b69.
Removing libmali as preferred provider due to CR-1052821
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Previously we were using gdb 7.7.1 just for microblaze for compatibility
issues, now switching back to upstream version 8.3.1 and removing no
longer needed 7.7.1 bb files and patches
Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
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This reverts commit 03115b3c35560617b2ffa9e911a6c1071ff6ad30.
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Temporarily removing preferred provider overrides for mali backed to
bypass mali packaging issues
for ex:
Multiple shlib providers for libMali.so.9
QA Issue: /usr/lib/libQt5EglFSDeviceIntegration.so.5.13.2 contained in
package qtbase requires libMali.so.9()(64bit), but no providers found in
RDEPENDS_qtbase? [file-rdeps]
Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
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Rename include file from arch-armv8.inc -> arch-armv8a.inc
Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
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Set default SOC_VARIANT for all versal machines as s80.
Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
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Adding base required dependencies to do_image_wic[depends] to make sure
the common files required to boot.bin have been deployed in DEPLOYDIR
before the do_image_wic task tries to use them.
zynqmp/versal will add virtual/kernel, virtual/boot-bin,
virtual/bootloader, and virtual/arm-trusted-firmware
zynq will add everything but virtual/arm-trusted-firmware
If you want to add other files to IMAGE_BOOT_FILES, aside from files
deployed from virtual/kernel, virtual/boot-bin, virtual/bootloader, you
may need to manually add the dependency to do_image_wic[depends]
Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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provider
Python3 package from OE-core depends on qemu-helper-native, to meet this
dependency use qemu-xilinx-helper-native as preferred provider. In
addition this helps the sstate-cache to be similar across generic
machines and evaluation boards.
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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Deploy u-boot.elf for Versal devices
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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While enabling PIE does not produce build time errors AFAIC, for
example: bash fails to return/exit properly when PIE is enabled.
Given the fact that init code relies on bash to source scripts at boot
time and such, booting hangs at init on microblaze targets.
Disable PIE on SECURITY_CFLAGS/SECURITY_LDFLAGS for MB architecture
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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Introduce FPGA_MNGR_RECONFIG_ENABLE to enable overlay configuration for
fpga-manager support in kernel.
To enable, set FPGA_MNGR_RECONFIG_ENABLE = "1" in local.conf or other
bitbake configuration files.
For backward compatibility, set FPGA_MNGR_RECONFIG_ENABLE based on
IMAGE_FEATURES.
In future release, the option of fpga-manager in IMAGE_FEATURES will be
deprecated.
Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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CONFIG_REMAKE_ELF is enabled for all zynq boards. Also, using
CONFIG_OF_SEPERATE is recommeneded by u-boot release v2019.01. So,
Deploy u-boot.elf instead of u-boot as u-boot.elf contains dtb. This
would solve the following boot issue:
No valid device tree binary found - please append one to U-Boot binary,
use u-boot-dtb.bin or define CONFIG_OF_EMBED. For sandbox, use -d
<file.dtb> initcall sequence 00461b18 failed at call 004582e0 (err=-1)
Signed-off-by: Sreeja Vadakattu <svadakat@xilinx.com>
Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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Build zImage in addition to uImage, this is useful for jtag booting
purpose
Signed-off-by: Vineeth Chowdary Karumanchi <vineethchowz.chowdary@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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Use the updated arch-armv8a tune instead of the old tune file
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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As per the commit f24275598687bcec0252186cb1d9c54b426fef9f, this include
file is no longer required. Remove it from the layer
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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Remove the parsing of KERNEL_DEVICETREE as by default those values will
be populated into the IMAGE_BOOT_FILES variable.
Also add a note describing why wildcard patterns work in the QB_DTB
field.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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Add all available dtb sources to the IMAGE_BOOT_FILES variable. For
device-tree recipe generated dtbs the files available are only known
after they files are deployed, so a wildcard pattern is used for these
files. Note that this pattern appears before the kernel device trees due
to the preference to use custom non-kernel device trees where available.
This ordering is needed so that recipes like u-boot-zynq-uenv can pick
the first device tree to select as the default.
The kernel device trees are specifically selected based on the value of
KERNEL_DEVICETREE, this avoid the duplication of kernel image type
prefixed files along side having the actual files that the kernel
builds.
Additionally remove all instances of "${MACHINE}.dtb" as they no longer
need to be specified and are incorrect due to the nesting of the files
in the `devicetree` directory.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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Replace the definition of IMAGE_BOOT_FILES in machine-xilinx-board.inc
with the use of a function which automatically selects available images
that should be included. This includes the existing implementation of
`get_dtb_list` and replaces it with a function that covers all image
files including the existing default for KERNEL_IMAGETYPE(S) and
UBOOT_BINARY.
Also remove the use of `get_dtb_list` from individual machines which is
replaced by the default value.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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IMAGE_BOOT_FILES
Replaced the hard-coded devicetree files in IMAGE_BOOT_FILES with a function,
which formats the KERNEL_DEVICETREE list properly.
Signed-off-by: Franz Forstmayr <f.forstmayr@gmail.com>
Reviewed-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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Add tune file supporting versal devices.
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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zynqmpeg and zynqmpev devices has Mali400, overrides extended with
mali400.This patch sets preferred providers to libmali-xlnx.
Signed-off-by: Vineeth Chowdary Karumanchi <vineethchowz.chowdary@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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components
The zynqmp-pmu class was being used to build standalone components (PMU)
for several devices, with the introduction of the meta-xilinx-standalone
layer and the xilinx-standalone distro, this is not necessary anymore.
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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zynq-7000 devices are mainly shipped in 2 variants.
https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
Available SOC_VARIANT's for zynq:
"7zs" - Zynq-7000 Single A9 Core
"7z" - Zynq-7000 Dual A9 Core
This will extend MACHINEOVERRIDES for each device variant as:
7zs --> zynq7zs
7z --> zynq7z
This patch sets the default value of SOC_VARIANT to 7z. This can be
overriden in machine configuration to match the intended FPGA device.
Signed-off-by: Vineeth Chowdary Karumanchi <vineethchowz.chowdary@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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UltraScale MPSoC is shipped in 3 device variants.
https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html#productTable
Available SOC_VARIANT's for zynqmp:
"cg" - Zynq UltraScale+ CG Devices
"eg" - Zynq UltraScale+ EG Devices (MALI 400)
"ev" - Zynq UltraScale+ EV Devices (MALI 400 + VCU)
This will extend MACHINEOVERRIDES for each device variant as:
cg --> zynqmpcg
eg --> zynqmpeg
ev --> zynqmpev
This patch sets the default value of SOC_VARIANT to eg. This can be
overriden in machine configuration to match the intended FPGA device.
Signed-off-by: Vineeth Chowdary Karumanchi <vineethchowz.chowdary@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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features
This patch enables to add overrides depending on the SoC capabilities.
UltraScale+ FPGA has different variants of silicon to support different
features like MALI400, VCU. Categorically there are three variants: cg
devices, eg devices(MALI 400) and ev devices (MALI 400+ VCU)
See:
https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html#productTable
dr devices are based for UltraScale+ RFSoC
This patch allows machineoverides to be extended as zynqmp(cg|eg|ev|dr)
and mali400/vcu (based on functionality). This helps in grouping of
settings for similar SoC
This patch also adds packages to be a part of the feed based on
SOC_FAMILY and SOC_VARIANT
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
Signed-off-by: Vineeth Chowdary Karumanchi <vineethchowz.chowdary@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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The MicroBlaze tunes are now part of oe-core. This removes the need for
the meta-xilinx-bsp layer to provide architecture tunes.
The tunes in oe-core are almost identical (with the exception of
tune-microblaze.inc which had machine configuration in meta-xilinx).
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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With the perspective removal of tune-microblaze.inc, the following
preferred GDB version configuration for MicroBlaze needs to be
relocated.
This change also drops the setting of gdb-cross* targets as they were
not setup properly since "gdb-cross-${TARGET_ARCH}" was not specified
correctly. This is also preferred as newer GDB (e.g. 8.0) does support
gdb-cross for debugging (just not gdbserver/gdb).
Ideally the MicroBlaze GDB patches should be updated to support the
newest GDB and or upstreamed. However this setup continues to be
available until that occurs.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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The tune-microblaze.inc is currently providing this configuration,
however since this is not a tune specific configuration it should be set
by the machine itself. Additionally with the perspective change to
remove tune-microblaze.inc the reliance on this includes configuration
needs to be removed.
Also remove the superfluous '_remove = "device-tree"' for
s3adsp1800-qemu-microblazeeb.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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With prelink-rtld support available for MicroBlaze and toolchain fixes
for atomic CAS bugs it is functional to generate gobject introspection
data for MicroBlaze binaries. This does still require the meta-xilinx
append for qemu which enables the architecture such that qemu linux user
is available.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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As discussed previously on mailing list, we are proceeding with layer
restructuring. For rocko release we will have the following layers
meta-xilinx
->meta-xilinx-bsp (current meta-xilinx)
->meta-xilinx-contrib
In the subsequent releases we will add other layers from Xilinx
meta-xilinx
->meta-xilinx-bsp (current meta-xilinx)
->meta-petalinux
->meta-xilinx-tools
->meta-xilinx-contrib
This will provide one clone to get all the required meta layers from
Xilinx for a complete solution, and the users can blacklist any layer
which they don't want to use using bblayer.conf.
This will enables us to help our vendors/partners to add their reference
designs, board definitions etc.
Recipe changes :
* Move reference design zybo-linux-bd.bb to meta-xilinx-contrib
* Move kernel patches realted to zybo-linux-bd-zynq7 board to
meta-xilinx-contrib
* Update README
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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