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From: Ricardo Salveti de Araujo <ricardo.salveti@linaro.org>
To: x-loader@googlegroups.com
Cc: patches@linaro.org,
	Ricardo Salveti de Araujo <ricardo.salveti@linaro.org>
Subject: [x-loader] [PATCH v2] omap4: pandaboard: ehci fref_clkout per board revision
Date: Mon, 11 Jul 2011 04:39:17 -0300
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Add support for correctly configuring the fref_clkout depending on the
board revision of the pandaboard. This patch is necessary to make u-boot
work with the smsc usb+ethernet driver.

Tested USB+Eth with TFTP and PXE using linaro u-boot:
http://git.linaro.org/gitweb?p=boot/u-boot-linaro-stable.git;a=summary

Based on patch from David Anders <x0132446@ti.com> from
omap4_panda_L24.9 branch at gitorious.org/pandaboard x-loader tree.

Changes since v1:
 * Moving the code from s_init instead of adding a new block

Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@linaro.org>
---
 board/omap4430panda/omap4430panda.c |   58 +++++++++++++++-------------------
 1 files changed, 26 insertions(+), 32 deletions(-)

diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c
index 9b4e457..bcee6fe 100644
--- a/board/omap4430panda/omap4430panda.c
+++ b/board/omap4430panda/omap4430panda.c
@@ -531,6 +531,7 @@ static void ddr_init(void)
  *****************************************/
 int board_init(void)
 {
+	unsigned int rev = omap_revision();
 	unsigned int v;
 
 	/*
@@ -546,10 +547,32 @@ int board_init(void)
 	v = __raw_readl(OMAP44XX_GPIO_BASE2 + __GPIO_DATAOUT);
 	__raw_writel((v & ~(1 << 30)), OMAP44XX_GPIO_BASE2 + __GPIO_DATAOUT);
 
-	/* kill USB PLL */
+	if (rev == OMAP4430_ES1_0)
+		return 0;
 
-	v = __raw_readl(CM_CLKMODE_DPLL_USB);
-	__raw_writel((v & ~7) | 1, CM_CLKMODE_DPLL_USB);
+	if (__raw_readl(OMAP44XX_GPIO_BASE6 + __GPIO_DATAIN) & (1 << 22)) {
+		/* enable software ioreq */
+		sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1);
+		/* set for sys_clk (38.4MHz) */
+		sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0);
+		/* set divisor to 2 */
+		sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x1);
+		/* set the clock source to active */
+		sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
+		/* enable clocks */
+		sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
+	} else {
+		/* enable software ioreq */
+		sr32(OMAP44XX_SCRM_AUXCLK1, 8, 1, 0x1);
+		/* set for PER_DPLL */
+		sr32(OMAP44XX_SCRM_AUXCLK1, 1, 2, 0x2);
+		/* set divisor to 16 */
+		sr32(OMAP44XX_SCRM_AUXCLK1, 16, 4, 0xf);
+		/* set the clock source to active */
+		sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
+		/* enable clocks */
+		sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
+	}
 
 	return 0;
 }
@@ -683,8 +706,6 @@ static int scale_vcores(void)
 
 void s_init(void)
 {
-	unsigned int rev = omap_revision();
-
 	/*
 	 * this is required to survive the muxconf in the case the ROM
 	 * started up USB OTG
@@ -707,33 +728,6 @@ void s_init(void)
 	/* setup_auxcr(get_device_type(), external_boot); */
 
 	ddr_init();
-
-	if (rev == OMAP4430_ES1_0)
-		return;
-
-	if (__raw_readl(OMAP44XX_GPIO_BASE6 + __GPIO_DATAIN) & (1 << 22)) {
-		/* enable software ioreq */
-		sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1);
-		/* set for sys_clk (38.4MHz) */
-		sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0);
-		/* set divisor to 2 */
-		sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x1);
-		/* set the clock source to active */
-		sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
-		/* enable clocks */
-		sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
-	} else {
-		/* enable software ioreq */
-		sr32(OMAP44XX_SCRM_AUXCLK1, 8, 1, 0x1);
-		/* set for PER_DPLL */
-		sr32(OMAP44XX_SCRM_AUXCLK1, 1, 2, 0x2);
-		/* set divisor to 16 */
-		sr32(OMAP44XX_SCRM_AUXCLK1, 16, 4, 0xf);
-		/* set the clock source to active */
-		sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
-		/* enable clocks */
-		sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
-	}
 }
 
 /*******************************************************
-- 
1.7.4.1

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