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Diffstat (limited to 'recipes-bsp/u-boot/u-boot-v2012.04.01/0005-MX53-Add-support-to-ESG-ima3-board.patch')
-rw-r--r--recipes-bsp/u-boot/u-boot-v2012.04.01/0005-MX53-Add-support-to-ESG-ima3-board.patch781
1 files changed, 781 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0005-MX53-Add-support-to-ESG-ima3-board.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0005-MX53-Add-support-to-ESG-ima3-board.patch
new file mode 100644
index 0000000..25114ca
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot-v2012.04.01/0005-MX53-Add-support-to-ESG-ima3-board.patch
@@ -0,0 +1,781 @@
+From 4b78125dda9413f121aadc8ddb3a2ae2238de006 Mon Sep 17 00:00:00 2001
+From: Stefano Babic <sbabic@denx.de>
+Date: Wed, 22 Feb 2012 00:24:40 +0000
+Subject: [PATCH 05/56] MX53: Add support to ESG ima3 board
+
+The ESG ima3-mx53 board is based on the Freescale
+i.MX53 SOC. It boots from NOR (128 MB) and
+supports Ethernet (FEC), SATA.
+
+Signed-off-by: Stefano Babic <sbabic@denx.de>
+---
+ board/esg/ima3-mx53/Makefile | 41 ++++++
+ board/esg/ima3-mx53/ima3-mx53.c | 302 ++++++++++++++++++++++++++++++++++++++
+ board/esg/ima3-mx53/imximage.cfg | 108 ++++++++++++++
+ boards.cfg | 1 +
+ include/configs/ima3-mx53.h | 269 +++++++++++++++++++++++++++++++++
+ 5 files changed, 721 insertions(+)
+ create mode 100644 board/esg/ima3-mx53/Makefile
+ create mode 100644 board/esg/ima3-mx53/ima3-mx53.c
+ create mode 100644 board/esg/ima3-mx53/imximage.cfg
+ create mode 100644 include/configs/ima3-mx53.h
+
+diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile
+new file mode 100644
+index 0000000..f3b13bc
+--- /dev/null
++++ b/board/esg/ima3-mx53/Makefile
+@@ -0,0 +1,41 @@
++#
++# Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
++#
++# Based on ti/evm/Makefile
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).o
++
++COBJS := ima3-mx53.o
++
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++
++$(LIB): $(obj).depend $(OBJS)
++ $(call cmd_link_o_target, $(OBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c
+new file mode 100644
+index 0000000..9ecf31d
+--- /dev/null
++++ b/board/esg/ima3-mx53/ima3-mx53.c
+@@ -0,0 +1,302 @@
++/*
++ * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
++ *
++ * (C) Copyright 2010 Freescale Semiconductor, Inc.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.
++ */
++#include <common.h>
++#include <asm/io.h>
++#include <asm/arch/imx-regs.h>
++#include <asm/arch/mx5x_pins.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/arch/crm_regs.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/iomux.h>
++#include <asm/errno.h>
++#include <netdev.h>
++#include <mmc.h>
++#include <fsl_esdhc.h>
++#include <asm/gpio.h>
++
++/* NOR flash configuration */
++#define IMA3_MX53_CS0GCR1 (CSEN | DSZ(2))
++#define IMA3_MX53_CS0GCR2 0
++#define IMA3_MX53_CS0RCR1 (RCSN(2) | OEN(1) | RWSC(15))
++#define IMA3_MX53_CS0RCR2 0
++#define IMA3_MX53_CS0WCR1 (WBED1 | WCSN(2) | WEN(1) | WWSC(15))
++#define IMA3_MX53_CS0WCR2 0
++
++DECLARE_GLOBAL_DATA_PTR;
++
++static void weim_nor_settings(void)
++{
++ struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
++
++ writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1);
++ writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2);
++ writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1);
++ writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2);
++ writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1);
++ writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2);
++ writel(0x0, &weim_regs->wcr);
++
++ set_chipselect_size(CS0_128);
++}
++
++int dram_init(void)
++{
++ gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
++ PHYS_SDRAM_1_SIZE);
++ return 0;
++}
++
++static void setup_iomux_uart(void)
++{
++ /* UART4 RXD */
++ mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2);
++ mxc_iomux_set_pad(MX53_PIN_CSI0_D13,
++ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
++ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
++ PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
++ mxc_iomux_set_input(MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
++
++ /* UART4 TXD */
++ mxc_request_iomux(MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT2);
++ mxc_iomux_set_pad(MX53_PIN_CSI0_D12,
++ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
++ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
++ PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
++}
++
++static void setup_iomux_fec(void)
++{
++ /*FEC_MDIO*/
++ mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
++ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
++ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU |
++ PAD_CTL_ODE_OPENDRAIN_ENABLE);
++ mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
++
++ /*FEC_MDC*/
++ mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
++
++ /* FEC RXD3 */
++ mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6);
++ mxc_iomux_set_pad(MX53_PIN_KEY_COL0, PAD_CTL_HYS_ENABLE |
++ PAD_CTL_PKE_ENABLE);
++
++ /* FEC RXD2 */
++ mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6);
++ mxc_iomux_set_pad(MX53_PIN_KEY_COL2, PAD_CTL_HYS_ENABLE |
++ PAD_CTL_PKE_ENABLE);
++
++ /* FEC RXD1 */
++ mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, PAD_CTL_HYS_ENABLE |
++ PAD_CTL_PKE_ENABLE);
++
++ /* FEC RXD0 */
++ mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, PAD_CTL_HYS_ENABLE |
++ PAD_CTL_PKE_ENABLE);
++
++ /* FEC TXD3 */
++ mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6);
++ mxc_iomux_set_pad(MX53_PIN_GPIO_19, PAD_CTL_DRV_HIGH);
++
++ /* FEC TXD2 */
++ mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6);
++ mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH);
++
++ /* FEC TXD1 */
++ mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
++
++ /* FEC TXD0 */
++ mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
++
++ /* FEC TX_EN */
++ mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
++
++ /* FEC TX_CLK */
++ mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, PAD_CTL_HYS_ENABLE |
++ PAD_CTL_PKE_ENABLE);
++
++ /* FEC RX_ER */
++ mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, PAD_CTL_HYS_ENABLE |
++ PAD_CTL_PKE_ENABLE);
++
++ /* FEC RX_DV */
++ mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, PAD_CTL_HYS_ENABLE |
++ PAD_CTL_PKE_ENABLE);
++
++ /* FEC CRS */
++ mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6);
++ mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_HYS_ENABLE |
++ PAD_CTL_PKE_ENABLE);
++
++ /* FEC COL */
++ mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6);
++ mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, PAD_CTL_HYS_ENABLE |
++ PAD_CTL_PKE_ENABLE);
++ mxc_iomux_set_input(MX53_FEC_FEC_COL_SELECT_INPUT, 0x0);
++
++ /* FEC RX_CLK */
++ mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6);
++ mxc_iomux_set_pad(MX53_PIN_KEY_COL1, PAD_CTL_HYS_ENABLE |
++ PAD_CTL_PKE_ENABLE);
++ mxc_iomux_set_input(MX53_FEC_FEC_RX_CLK_SELECT_INPUT, 0x0);
++}
++
++#ifdef CONFIG_FSL_ESDHC
++struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR, 1 };
++
++int board_mmc_getcd(struct mmc *mmc)
++{
++ int ret;
++
++ ret = !gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
++
++ return ret;
++}
++
++int board_mmc_init(bd_t *bis)
++{
++ mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
++ mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
++ mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
++ mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
++ mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
++ mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
++ mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
++ mxc_iomux_set_pad(MX53_PIN_GPIO_1,
++ PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
++ PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
++ PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE);
++ gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
++
++ mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
++ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
++ PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
++ mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
++ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
++ PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH);
++ mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
++ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
++ PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
++ mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
++ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
++ PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
++ mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
++ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
++ PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
++ mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
++ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
++ PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
++
++ return fsl_esdhc_initialize(bis, &esdhc_cfg);
++}
++#endif
++
++static void setup_iomux_spi(void)
++{
++ /* SCLK */
++ mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT3);
++ mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
++ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
++ PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
++ mxc_iomux_set_input(MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x1);
++ /* MOSI */
++ mxc_request_iomux(MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT3);
++ mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
++ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
++ PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
++ mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, 0x1);
++ /* MISO */
++ mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT3);
++ mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
++ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
++ PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
++ mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, 0x1);
++ /* SSEL 0 */
++ mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_GPIO);
++ mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
++ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
++ PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
++ gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11), 1);
++}
++
++int board_early_init_f(void)
++{
++ /* configure I/O pads */
++ setup_iomux_uart();
++ setup_iomux_fec();
++
++ weim_nor_settings();
++
++ /* configure spi */
++ setup_iomux_spi();
++
++ return 0;
++}
++
++int board_init(void)
++{
++ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
++
++ mxc_set_sata_internal_clock();
++
++ return 0;
++}
++
++#if defined(CONFIG_RESET_PHY_R)
++#include <miiphy.h>
++
++void reset_phy(void)
++{
++ unsigned short reg;
++
++ /* reset the phy */
++ miiphy_reset("FEC", CONFIG_PHY_ADDR);
++
++ /* set hard link to 100Mbit, full-duplex */
++ miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, &reg);
++ reg &= ~BMCR_ANENABLE;
++ reg |= (BMCR_SPEED100 | BMCR_FULLDPLX);
++ miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg);
++
++ miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, &reg);
++ reg |= (1 << 5);
++ miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg);
++}
++#endif
++
++int checkboard(void)
++{
++ puts("Board: IMA3_MX53\n");
++
++ return 0;
++}
+diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg
+new file mode 100644
+index 0000000..fa6b42d
+--- /dev/null
++++ b/board/esg/ima3-mx53/imximage.cfg
+@@ -0,0 +1,108 @@
++#
++# (C) Copyright 2012
++# Stefano Babic DENX Software Engineering sbabic@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not write to the Free Software
++# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
++# MA 02110-1301 USA
++#
++# Refer docs/README.imxmage for more details about how-to configure
++# and create imximage boot image
++#
++# The syntax is taken as close as possible with the kwbimage
++
++# image version
++
++IMAGE_VERSION 2
++
++# Boot Device : one of
++# spi, sd (the board has no nand neither onenand)
++
++BOOT_FROM nor
++
++# Device Configuration Data (DCD)
++#
++# Each entry must have the format:
++# Addr-type Address Value
++#
++# where:
++# Addr-type register length (1,2 or 4 bytes)
++# Address absolute address of the register
++# value value to be stored in the register
++
++# IOMUX for RAM only
++DATA 4 0x53fa8554 0x300020
++DATA 4 0x53fa8560 0x300020
++DATA 4 0x53fa8594 0x300020
++DATA 4 0x53fa8584 0x300020
++DATA 4 0x53fa8558 0x300040
++DATA 4 0x53fa8568 0x300040
++DATA 4 0x53fa8590 0x300040
++DATA 4 0x53fa857c 0x300040
++DATA 4 0x53fa8564 0x300040
++DATA 4 0x53fa8580 0x300040
++DATA 4 0x53fa8570 0x300220
++DATA 4 0x53fa8578 0x300220
++DATA 4 0x53fa872c 0x300000
++DATA 4 0x53fa8728 0x300000
++DATA 4 0x53fa871c 0x300000
++DATA 4 0x53fa8718 0x300000
++DATA 4 0x53fa8574 0x300020
++DATA 4 0x53fa8588 0x300020
++DATA 4 0x53fa855c 0x0
++DATA 4 0x53fa858c 0x0
++DATA 4 0x53fa856c 0x300040
++DATA 4 0x53fa86f0 0x300000
++DATA 4 0x53fa8720 0x300000
++DATA 4 0x53fa86fc 0x0
++DATA 4 0x53fa86f4 0x0
++DATA 4 0x53fa8714 0x0
++DATA 4 0x53fa8724 0x4000000
++#
++# DDR RAM
++DATA 4 0x63fd9088 0x40404040
++DATA 4 0x63fd9090 0x40404040
++DATA 4 0x63fd907C 0x01420143
++DATA 4 0x63fd9080 0x01450146
++DATA 4 0x63fd9018 0x00111740
++DATA 4 0x63fd9000 0x84190000
++# esdcfgX
++DATA 4 0x63fd900C 0x9f5152e3
++DATA 4 0x63fd9010 0xb68e8a63
++DATA 4 0x63fd9014 0x01ff00db
++# Read/Write command delay
++DATA 4 0x63fd902c 0x000026d2
++# Out of reset delays
++DATA 4 0x63fd9030 0x00ff0e21
++# ESDCTL ODT timing control
++DATA 4 0x63fd9008 0x12273030
++# ESDCTL power down control
++DATA 4 0x63fd9004 0x0002002d
++# Set registers in DDR memory chips
++DATA 4 0x63fd901c 0x00008032
++DATA 4 0x63fd901c 0x00008033
++DATA 4 0x63fd901c 0x00028031
++DATA 4 0x63fd901c 0x052080b0
++DATA 4 0x63fd901c 0x04008040
++# ESDCTL refresh control
++DATA 4 0x63fd9020 0x00005800
++# PHY ZQ HW control
++DATA 4 0x63fd9040 0x05380003
++# PHY ODT control
++DATA 4 0x63fd9058 0x00022222
++# start DDR3
++DATA 4 0x63fd901c 0x00000000
+diff --git a/boards.cfg b/boards.cfg
+index 3cf75c3..93ecae6 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -189,6 +189,7 @@ mx53ard arm armv7 mx53ard freesca
+ mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg
+ mx53loco arm armv7 mx53loco freescale mx5 mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg
+ mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
++ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
+ vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
+ mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
+ mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/mx6qsabrelite/imximage.cfg
+diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h
+new file mode 100644
+index 0000000..ea48d64
+--- /dev/null
++++ b/include/configs/ima3-mx53.h
+@@ -0,0 +1,269 @@
++/*
++ * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
++ *
++ * Copyright (C) 2010 Freescale Semiconductor, Inc.
++ *
++ * Configuration settings for the MX53-EVK Freescale board.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++/* SOC type must be included before imx-regs.h */
++#define CONFIG_MX53
++#include <asm/arch/imx-regs.h>
++#include <asm/arch/mx5x_pins.h>
++
++#define CONFIG_SYS_MX5_HCLK 24000000
++#define CONFIG_SYS_MX5_CLK32 32768
++
++#define CONFIG_DISPLAY_CPUINFO
++#define CONFIG_DISPLAY_BOARDINFO
++
++#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
++#define CONFIG_SETUP_MEMORY_TAGS
++#define CONFIG_INITRD_TAG
++
++#define CONFIG_OF_LIBFDT
++
++/* Size of malloc() pool */
++#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
++
++#define CONFIG_BOARD_EARLY_INIT_F
++
++/* Enable GPIOs */
++#define CONFIG_MXC_GPIO
++
++/* UART */
++#define CONFIG_MXC_UART
++#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
++
++/* MMC */
++#define CONFIG_FSL_ESDHC
++#define CONFIG_SYS_FSL_ESDHC_ADDR 0
++#define CONFIG_SYS_FSL_ESDHC_NUM 1
++
++#define CONFIG_MMC
++#define CONFIG_GENERIC_MMC
++#define CONFIG_DOS_PARTITION
++
++/* Ethernet on FEC */
++#define CONFIG_NET_MULTI
++#define CONFIG_MII
++#define CONFIG_DISCOVER_PHY
++
++#define CONFIG_FEC_MXC
++#define IMX_FEC_BASE FEC_BASE_ADDR
++#define CONFIG_FEC_MXC_PHYADDR 0x01
++#define CONFIG_PHY_ADDR CONFIG_FEC_MXC_PHYADDR
++#define CONFIG_RESET_PHY_R
++#define CONFIG_FEC_MXC_NO_ANEG
++#define CONFIG_PRIME "FEC0"
++
++/* SPI */
++#define CONFIG_HARD_SPI
++#define CONFIG_MXC_SPI
++#define CONFIG_DEFAULT_SPI_BUS 1
++#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
++
++/* SPI FLASH - not used for environment */
++#define CONFIG_SPI_FLASH
++#define CONFIG_SPI_FLASH_STMICRO
++#define CONFIG_SPI_FLASH_CS (IOMUX_TO_GPIO(MX53_PIN_CSI0_D11) \
++ << 8) | 0
++#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
++#define CONFIG_SF_DEFAULT_SPEED 25000000
++
++/* allow to overwrite serial and ethaddr */
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_CONS_INDEX 1
++#define CONFIG_BAUDRATE 115200
++#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
++
++/* Command definition */
++#include <config_cmd_default.h>
++#define CONFIG_CMD_PING
++#define CONFIG_CMD_DHCP
++#define CONFIG_CMD_MII
++#define CONFIG_CMD_MMC
++#define CONFIG_CMD_FAT
++#define CONFIG_CMD_EXT2
++#define CONFIG_CMD_MTDPARTS
++#define CONFIG_CMD_SPI
++#define CONFIG_CMD_SF
++#define CONFIG_CMD_GPIO
++
++#define CONFIG_BOOTDELAY 3
++
++#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
++#define CONFIG_SYS_TEXT_BASE 0xf0001400 /* uboot in nor flash */
++
++#define CONFIG_ARP_TIMEOUT 200UL
++
++/* Miscellaneous configurable options */
++#define CONFIG_SYS_LONGHELP /* undef to save memory */
++#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
++#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
++#define CONFIG_SYS_PROMPT "IMA3 MX53 U-Boot > "
++#define CONFIG_AUTO_COMPLETE
++#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
++
++/* Print Buffer Size */
++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
++#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
++
++#define CONFIG_SYS_MEMTEST_START 0x70000000
++#define CONFIG_SYS_MEMTEST_END 0x10000
++
++#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
++
++#define CONFIG_SYS_HZ 1000
++#define CONFIG_CMDLINE_EDITING
++
++/* Stack sizes */
++#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
++
++/* Physical Memory Map */
++#define CONFIG_NR_DRAM_BANKS 1
++#define PHYS_SDRAM_1 CSD0_BASE_ADDR
++#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
++
++#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
++#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
++#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
++
++#define CONFIG_SYS_INIT_SP_OFFSET \
++ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
++#define CONFIG_SYS_INIT_SP_ADDR \
++ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
++
++#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
++#define MTDIDS_DEFAULT "nor0=f0000000.flash"
++
++/* FLASH and environment organization */
++
++#define CONFIG_SYS_FLASH_BASE 0xF0000000
++#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
++#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
++#define CONFIG_FLASH_CFI_MTD /* with MTD support */
++#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
++#define CONFIG_SYS_MAX_FLASH_BANKS 1
++#define CONFIG_SYS_MAX_FLASH_SECT 1024
++
++#define CONFIG_SYS_FLASH_EMPTY_INFO
++#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
++
++#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
++#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
++
++#define CONFIG_ENV_SIZE (8 * 1024)
++#define CONFIG_ENV_IS_IN_FLASH
++#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
++ CONFIG_SYS_MONITOR_LEN)
++#define CONFIG_ENV_SECT_SIZE 0x20000
++#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
++ CONFIG_ENV_SECT_SIZE)
++#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
++
++/*
++ * Default environment and default scripts
++ * to update uboot and load kernel
++ */
++
++#define HOSTNAME ima3-mx53
++#define xstr(s) str(s)
++#define str(s) #s
++
++#define CONFIG_HOSTNAME ima3-mx53
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "netdev=eth0\0" \
++ "nfsargs=setenv bootargs root=/dev/nfs rw " \
++ "nfsroot=${serverip}:${rootpath}\0" \
++ "ramargs=setenv bootargs root=/dev/ram0 rw\0" \
++ "addip_sta=setenv bootargs ${bootargs} " \
++ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
++ ":${hostname}:${netdev}:off panic=1\0" \
++ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
++ "addip=if test -n ${ipdyn};then run addip_dyn;" \
++ "else run addip_sta;fi\0" \
++ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
++ "addtty=setenv bootargs ${bootargs}" \
++ " console=${console},${baudrate}\0" \
++ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
++ "console=ttymxc3\0" \
++ "loadaddr=70800000\0" \
++ "kernel_addr_r=70800000\0" \
++ "ramdisk_addr_r=71000000\0" \
++ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
++ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
++ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
++ "mmcargs=setenv bootargs root=${mmcroot} " \
++ "rootfstype=${mmcrootfstype}\0" \
++ "mmcroot=/dev/mmcblk0p3 rw\0" \
++ "mmcboot=echo Booting from mmc ...; " \
++ "run mmcargs addip addtty addmtd addmisc mmcload;" \
++ "bootm\0" \
++ "mmcload=fatload mmc ${mmcdev}:${mmcpart} " \
++ "${loadaddr} ${uimage}\0" \
++ "mmcrootfstype=ext3 rootwait\0" \
++ "flash_self=run ramargs addip addtty addmtd addmisc;" \
++ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
++ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
++ "bootm ${kernel_addr}\0" \
++ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
++ "run nfsargs addip addtty addmtd addmisc;" \
++ "bootm ${kernel_addr_r}\0" \
++ "net_self_load=tftp ${ramdisk_addr_r} ${ramdisk_file};" \
++ "tftp ${kernel_addr_r} ${bootfile}\0" \
++ "net_self=if run net_self_load;then " \
++ "run ramargs addip addtty addmtd addmisc;" \
++ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
++ "else echo Images not loades;fi\0" \
++ "satargs=setenv bootargs root=/dev/sda1\0" \
++ "satafile=boot/uImage\0" \
++ "ssdboot=echo Booting from ssd ...; " \
++ "run satargs addip addtty addmtd addmisc;" \
++ "sata init;ext2load sata 0:1 ${kernel_addr_r} " \
++ "${satafile};bootm\0" \
++ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.imx\0" \
++ "uimage=uImage\0" \
++ "load=tftp ${loadaddr} ${u-boot}\0" \
++ "uboot_addr=0xf0001000\0" \
++ "update=protect off 0xf0000000 +60000;" \
++ "erase ${uboot_addr} +60000;" \
++ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
++ "upd=if run load;then echo Updating u-boot;if run update;" \
++ "then echo U-Boot updated;" \
++ "else echo Error updating u-boot !;" \
++ "echo Board without bootloader !!;" \
++ "fi;" \
++ "else echo U-Boot not downloaded..exiting;fi\0" \
++ "bootcmd=run net_nfs\0"
++
++
++#define CONFIG_CMD_SATA
++#ifdef CONFIG_CMD_SATA
++ #define CONFIG_DWC_AHSATA
++ #define CONFIG_SYS_SATA_MAX_DEVICE 1
++ #define CONFIG_DWC_AHSATA_PORT_ID 0
++ #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
++ #define CONFIG_LBA48
++ #define CONFIG_LIBATA
++#endif
++
++#endif /* __CONFIG_H */
+--
+1.7.10
+
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