blob: 5b24b5c1b206dcea61112af801d06c3329663962 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
|
From 148030d491eb0bc69792e800291ee61722ad1a51 Mon Sep 17 00:00:00 2001
From: "Philip.Cox@amd.com" <Philip.Cox@amd.com>
Date: Tue, 26 Nov 2019 14:28:24 -0500
Subject: [PATCH 4644/4736] drm/amdkfd: kfd debugger -- set DISPATCH_PTR
We need to set bit 14 in mqd var CP_HQD_HQ_STATUS0 to have the CP set
the DISPATCH_PTR which is needed for the debugger.
Bug: SWDEV-208421
Change-Id: I2b98afc392a9299210aa2b6faa00fc83b27e51eb
Signed-off-by: Philip.Cox@amd.com <Philip.Cox@amd.com>
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index f9ee530774bf..1b35cad950b4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -193,6 +193,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
+ /* Set cp_hqd_hq_status0 bit 14 to 1 to have the CP set up the
+ * DISPATCH_PTR. This is required for the kfd debugger
+ */
+ m->cp_hqd_hq_status0 = 1 << 14;
+
if (q->format == KFD_QUEUE_FORMAT_AQL) {
m->cp_hqd_aql_control =
1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
--
2.17.1
|
