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From bcd12b314c04a6585ae32353612874158493f92d Mon Sep 17 00:00:00 2001
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Tue, 1 Oct 2019 11:01:00 -0400
Subject: [PATCH 4247/4736] drm/amd/display: fix number of dcn21 dpm clock
levels
These are specific to dcn21 and should not be increased for
reuse on other asics.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index 60d6620530a8..95f3193da951 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -245,8 +245,8 @@ struct pp_smu_funcs_nv {
#define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8
#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8
-#define PP_SMU_NUM_FCLK_DPM_LEVELS 8
-#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 8
+#define PP_SMU_NUM_FCLK_DPM_LEVELS 4
+#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4
struct dpm_clock {
uint32_t Freq; // In MHz
--
2.17.1
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