blob: 18aec7965f6a56b94d0d270df19f39b902b0b1a9 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
|
From 8c6d565627c82332119d70518dad00e9c362055f Mon Sep 17 00:00:00 2001
From: Harry Wentland <harry.wentland@amd.com>
Date: Tue, 29 May 2018 09:59:13 -0400
Subject: [PATCH 4557/5725] drm/amd/display: Fix wrong latency assignment for
VEGA clock levels
Also drop wrong 10kHz comment
Fixes: drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index ead3d21..d5e6b45 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -256,9 +256,8 @@ static void pp_to_dc_clock_levels_with_latency(
for (i = 0; i < clk_level_info->num_levels; i++) {
DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
- /* translate 10kHz to kHz */
clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
- clk_level_info->data[i].latency_in_us = pp_clks->data[i].clocks_in_khz;
+ clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
}
}
--
2.7.4
|