From b8e93c19d2aaa3d0f48a802dd779ca27e66236d2 Mon Sep 17 00:00:00 2001 From: Sanjay R Mehta Date: Thu, 13 Oct 2016 12:30:35 +0530 Subject: [PATCH 2/2] drm/amdgpu/gfx8: disable EDC Signed-off-by: Alex Deucher Signed-off-by: Sanjay R Mehta --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 92f3ee6..c5a3d04 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -1700,6 +1700,11 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) goto fail; } + /* read back registers to clear the counters */ + for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) + RREG32(sec_ded_counter_registers[i]); + +#if 0 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2); tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1); WREG32(mmGB_EDC_MODE, tmp); @@ -1708,10 +1713,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1; WREG32(mmCC_GC_EDC_CONFIG, tmp); - - /* read back registers to clear the counters */ - for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) - RREG32(sec_ded_counter_registers[i]); +#endif fail: fence_put(f); -- 2.7.4