From c0f19d299a31a816850d57d275d5fd7225844ac1 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Fri, 27 Sep 2019 12:24:05 -0400 Subject: [PATCH 4244/4736] drm/amd/display: Update min dcfclk [Why] NV12 has lower min dcfclk [How] Add update in update_bounding_box Signed-off-by: Alvin Lee Reviewed-by: Jun Lei Acked-by: Leo Li --- .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 0ef5c5d60f79..a094eac4dc95 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -3113,10 +3113,14 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s if (dc->bb_overrides.min_dcfclk_mhz > 0) min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; - else - // Accounting for SOC/DCF relationship, we can go as high as - // 506Mhz in Vmin. We need to code 507 since SMU will round down to 506. - min_dcfclk = 507; + else { + if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) + min_dcfclk = 310; + else + // Accounting for SOC/DCF relationship, we can go as high as + // 506Mhz in Vmin. + min_dcfclk = 506; + } for (i = 0; i < num_states; i++) { int min_fclk_required_by_uclk; -- 2.17.1