From f397a2e1a2e2d8e3857b5ba18de2c5a1a0bafc4a Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Tue, 25 Jun 2019 19:08:50 -0400 Subject: [PATCH 3552/4256] drm/amd/display: Add DFS reference clock field Add to clk_mgr_internal struct, for future use. Signed-off-by: Yongqiang Sun Reviewed-by: Yongqiang Sun Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index 9b6c885c0bba..7dd46eb96d67 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -216,6 +216,8 @@ struct clk_mgr_internal { bool dfs_bypass_enabled; /* True if the DFS-bypass feature is enabled and active. */ bool dfs_bypass_active; + + uint32_t dfs_ref_freq_khz; /* * Cache the display clock returned by VBIOS if DFS-bypass is enabled. * This is basically "Crystal Frequency In KHz" (XTALIN) frequency -- 2.17.1