From c85f9a88ca197481661880f8d3433f257ae8bdd2 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Wed, 14 Aug 2019 16:16:52 -0400 Subject: [PATCH 3460/4256] drm/amd/powerplay: add mode2 reset callback for pp_smu_mgr Also define reset modes (0, 1 and 2) Signed-off-by: Andrey Grodzovsky Alex Deucher Reviewed-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index 07fd64aad2ae..abeff1570277 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -189,6 +189,14 @@ struct phm_vce_clock_voltage_dependency_table { struct phm_vce_clock_voltage_dependency_record entries[1]; }; + +enum SMU_ASIC_RESET_MODE +{ + SMU_ASIC_RESET_MODE_0, + SMU_ASIC_RESET_MODE_1, + SMU_ASIC_RESET_MODE_2, +}; + struct pp_smumgr_func { char *name; int (*smu_init)(struct pp_hwmgr *hwmgr); @@ -345,6 +353,7 @@ struct pp_hwmgr_func { int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf); int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks); int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state); + int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode); }; struct pp_table_func { -- 2.17.1