From 889240d2028670d12f7533e670e3c7233ba196e4 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Wed, 17 Apr 2019 14:58:28 +0800 Subject: [PATCH 2341/2940] drm/amd/powerplay: add function get current clock freq interface for navi10 add function of get_current_clk_freq_by_table for navi10. Signed-off-by: Kevin Wang Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 ++++ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 24 +++++++++++++++++++ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 4 ++++ 3 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index 8ab9d259b453..4fc183bd0886 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -589,6 +589,9 @@ struct pptable_funcs { uint32_t *value); int (*set_watermarks_table)(struct smu_context *smu, void *watermarks, struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges); + int (*get_current_clk_freq_by_table)(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *value); }; struct smu_funcs @@ -881,6 +884,8 @@ struct smu_funcs ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL) #define smu_set_watermarks_table(smu, tab, clock_ranges) \ ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0) +#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \ + ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0) extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table, uint16_t *size, uint8_t *frev, uint8_t *crev, diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 8030c7a7edae..788bdf6dfac7 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -500,6 +500,29 @@ static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable) return 0; } +static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *value) +{ + static SmuMetrics_t metrics = {0}; + int ret = 0, clk_id = 0; + + if (!value) + return -EINVAL; + + ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false); + if (ret) + return ret; + + clk_id = smu_clk_get_index(smu, clk_type); + if (clk_id < 0) + return clk_id; + + *value = metrics.CurrClock[clk_id]; + + return ret; +} + static const struct pptable_funcs navi10_ppt_funcs = { .tables_init = navi10_tables_init, .alloc_dpm_context = navi10_allocate_dpm_context, @@ -514,6 +537,7 @@ static const struct pptable_funcs navi10_ppt_funcs = { .get_allowed_feature_mask = navi10_get_allowed_feature_mask, .set_default_dpm_table = navi10_set_default_dpm_table, .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable, + .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table, }; void navi10_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index 5d2e82ef250d..fc5df68df694 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -1084,6 +1084,10 @@ static int smu_v11_0_get_current_clk_freq(struct smu_context *smu, if (clk_id >= SMU_CLK_COUNT || !value) return -EINVAL; + /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */ + if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) == 0) + return smu_get_current_clk_freq_by_table(smu, clk_id, value); + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq, (smu_clk_get_index(smu, clk_id) << 16)); if (ret) -- 2.17.1