From 8abf8bd1bc6b675577c3353081830a20fa89e82e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 16 Aug 2018 13:23:48 +0200 Subject: [PATCH 1559/2940] drm/amdgpu: rework shadow handling during PD clear v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This way we only deal with the real BO in here. v2: use a do { ... } while loop instead v3: fix NULL pointer in v2 Signed-off-by: Christian König Reviewed-by: Felix Kuehling Acked-by: Huang Rui Signed-off-by: Chaudhary Amit Kumar --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 66 ++++++++++++++------------ 1 file changed, 35 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 6e96489900f1..e836d8fa639e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -766,44 +766,54 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) - goto error; + return r; r = amdgpu_ttm_alloc_gart(&bo->tbo); if (r) return r; - r = amdgpu_job_alloc_with_ib(adev, 64, &job); - if (r) - goto error; - - addr = amdgpu_bo_gpu_offset(bo); - if (ats_entries) { - uint64_t ats_value; + if (bo->shadow) { + r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement, + &ctx); + if (r) + return r; - ats_value = AMDGPU_PTE_DEFAULT_ATC; - if (level != AMDGPU_VM_PTB) - ats_value |= AMDGPU_PDE_PTE; + r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo); + if (r) + return r; - amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, - ats_entries, 0, ats_value); - addr += ats_entries * 8; - } + } - if (entries) { - uint64_t value = 0; + r = amdgpu_job_alloc_with_ib(adev, 64, &job); + if (r) + return r; + do { + addr = amdgpu_bo_gpu_offset(bo); + if (ats_entries) { + uint64_t ats_value; + + ats_value = AMDGPU_PTE_DEFAULT_ATC; + if (level != AMDGPU_VM_PTB) + ats_value |= AMDGPU_PDE_PTE; + + amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, + ats_entries, 0, ats_value); + addr += ats_entries * 8; + } - /* Workaround for fault priority problem on GMC9 */ - if (level == AMDGPU_VM_PTB && adev->asic_type >= CHIP_VEGA10) - value = AMDGPU_PTE_EXECUTABLE; + if (entries) { + uint64_t value = 0; - amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, - entries, 0, value); - } + amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, + entries, 0, value); + } + bo = bo->shadow; + }while (bo); amdgpu_ring_pad_ib(ring, &job->ibs[0]); WARN_ON(job->ibs[0].length_dw > 64); - r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv, + r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv, AMDGPU_FENCE_OWNER_UNDEFINED, false); if (r) goto error_free; @@ -813,19 +823,13 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, if (r) goto error_free; - amdgpu_bo_fence(bo, fence, true); + amdgpu_bo_fence(vm->root.base.bo, fence, true); dma_fence_put(fence); - if (bo->shadow) - return amdgpu_vm_clear_bo(adev, vm, bo->shadow, - level, pte_support_ats); - return 0; error_free: amdgpu_job_free(job); - -error: return r; } -- 2.17.1