From bd848e0a87b6ba9fdcd4146fe83b7d5eca497f66 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Mon, 21 Jan 2019 17:57:29 +0800 Subject: [PATCH 1125/2940] drm/amd/display: change the max clock level to 16 As the gfxclk for SMU11 can have at most 16 discrete levels. Signed-off-by: Evan Quan Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services_types.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index 9afd36a031a9..77200711abbe 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -92,7 +92,7 @@ enum dm_pp_clock_type { (clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \ "Invalid" -#define DM_PP_MAX_CLOCK_LEVELS 8 +#define DM_PP_MAX_CLOCK_LEVELS 16 struct dm_pp_clock_levels { uint32_t num_levels; -- 2.17.1