From 1bb69c86b3cde4aedb17ab3411cd9b9be671c9df Mon Sep 17 00:00:00 2001 From: Sudheesh Mavila Date: Mon, 4 Feb 2019 11:47:30 +0530 Subject: [PATCH 0611/2940] Revert "drm/amdgpu/gfx8: disable EDC to fix unigine heaven hang" This reverts commit c404fdabc1cbc3a626069ecf758dac3e7262f95b. --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index e56e492dc069..3d0f277a6523 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -1756,7 +1756,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); goto fail; } -#if 0 + tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2); tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1); WREG32(mmGB_EDC_MODE, tmp); @@ -1764,7 +1764,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) tmp = RREG32(mmCC_GC_EDC_CONFIG); tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1; WREG32(mmCC_GC_EDC_CONFIG, tmp); -#endif + /* read back registers to clear the counters */ for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) -- 2.17.1