From 98afeff8d1bfb86fe256e0320e641e606418e4e0 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 30 Oct 2018 10:38:41 +0800 Subject: [PATCH 5601/5725] drm/amdgpu: support Vega20 A1 ASICs Since they use different PSP firmwares from A0 ASICs for now. This will be dropped after they are unified to share the same PSP firmwares. Change-Id: I3bc8956dac62607e8771757858b1286a87f76cf3 Signed-off-by: Evan Quan Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index 3f3fac2..0a3f774 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -34,10 +34,13 @@ #include "nbio/nbio_7_4_offset.h" MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); +MODULE_FIRMWARE("amdgpu/vega20_sos_old.bin"); /* address block */ #define smnMP1_FIRMWARE_FLAGS 0x3010024 +#define VEGA20_BL_VERSION_VAR_NEW 0xA1 + static int psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) { @@ -99,6 +102,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) char fw_name[30]; int err = 0; const struct psp_firmware_header_v1_0 *hdr; + uint32_t bl_version; DRM_DEBUG("\n"); @@ -110,7 +114,13 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) BUG(); } - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); + bl_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_100); + bl_version = (bl_version & 0xFF0000) >> 16; + + if (bl_version == VEGA20_BL_VERSION_VAR_NEW) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos_old.bin", chip_name); err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); if (err) goto out; -- 2.7.4