From f591ba9a8b68b500bafec5f0c3c380cedf683cf2 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Tue, 12 Jun 2018 15:07:37 +0800 Subject: [PATCH 4646/5725] drm/amd/powerplay: Set higher SCLK&MCLK frequency than dpm7 in OD Fix the issue that SCLK&MCLK can't be set higher than dpm7 when OD is enabled in SMU7. Change-Id: If8249795739e29a063154cffce693b3c77cca151 Signed-off-by: Kenneth Feng Acked-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 46d6368..0f307a7 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -3761,7 +3761,10 @@ static int smu7_generate_dpm_level_enable_mask( const struct smu7_power_state *smu7_ps = cast_const_phw_smu7_power_state(states->pnew_state); - result = smu7_trim_dpm_states(hwmgr, smu7_ps); + /*skip the trim if od is enabled*/ + if (!hwmgr->od_enabled) + result = smu7_trim_dpm_states(hwmgr, smu7_ps); + if (result) return result; -- 2.7.4