From 61bf0a71e5b41abb7ed8eddfd2257c014caea6cc Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Fri, 20 Apr 2018 12:57:10 +0800 Subject: [PATCH 3336/4131] drm/amd/pp: Change pstate_clk frequency unit to 10KHz on Rv to keep consistent with other asics fix bug SWDEV-150537: RGP tool: Reported profiling clocks in RGP is not as expected Change-Id: I4a553dd0c85f30d1326fc4c38122d99d6383dc74 Reviewed-by: Evan Quan Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c index 8e10cc8..6feeff8 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c @@ -452,8 +452,8 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr) hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; - hwmgr->pstate_sclk = RAVEN_UMD_PSTATE_GFXCLK; - hwmgr->pstate_mclk = RAVEN_UMD_PSTATE_FCLK; + hwmgr->pstate_sclk = RAVEN_UMD_PSTATE_GFXCLK * 100; + hwmgr->pstate_mclk = RAVEN_UMD_PSTATE_FCLK * 100; return result; } -- 2.7.4