From d546e2eeb5765c622ac79a827dd123ed40738b43 Mon Sep 17 00:00:00 2001 From: Eric Bernstein Date: Tue, 31 Oct 2017 11:52:25 -0400 Subject: [PATCH 2713/4131] drm/amd/display: Add OPP DPG blank function Added a function to blank data using OPP DPG. Clean up code to prepare for pseudocode review with HW. Signed-off-by: Eric Bernstein Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 62 +++++++++++++++--------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 45 +++-------------- drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 6 +++ 3 files changed, 51 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index a136f70..71385a0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -38,6 +38,24 @@ oppn10->base.ctx +enum dpg_mode { + /* RGB colour block mode */ + DPG_MODE_RGB_COLOUR_BLOCK, + /* YCbCr-601 colour block mode */ + DPG_MODE_YCBCR_601_COLOUR_BLOCK, + /* YCbCr-709 colour block mode */ + DPG_MODE_YCBCR_709_COLOUR_BLOCK, + /* Vertical bar mode */ + DPG_MODE_VERTICAL_BAR, + /* Horizontal bar mode */ + DPG_MODE_HORIZONTAL_BAR, + /* Single ramp mode */ + DPG_MODE_RGB_SINGLE_RAMP, + /* Dual ramp mode */ + DPG_MODE_RGB_DUAL_RAMP, + /* RGB XR BIAS mode */ + DPG_MODE_RGB_XR_BIAS +}; /************* FORMATTER ************/ @@ -47,7 +65,7 @@ * 2) enable truncation * 3) HW remove 12bit FMT support for DCE11 power saving reason. */ -static void set_truncation( +static void opp1_set_truncation( struct dcn10_opp *oppn10, const struct bit_depth_reduction_params *params) { @@ -57,7 +75,7 @@ static void set_truncation( FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE); } -static void set_spatial_dither( +static void opp1_set_spatial_dither( struct dcn10_opp *oppn10, const struct bit_depth_reduction_params *params) { @@ -136,14 +154,14 @@ static void set_spatial_dither( FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM); } -static void oppn10_program_bit_depth_reduction( +static void opp1_program_bit_depth_reduction( struct output_pixel_processor *opp, const struct bit_depth_reduction_params *params) { struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - set_truncation(oppn10, params); - set_spatial_dither(oppn10, params); + opp1_set_truncation(oppn10, params); + opp1_set_spatial_dither(oppn10, params); /* TODO * set_temporal_dither(oppn10, params); */ @@ -156,7 +174,7 @@ static void oppn10_program_bit_depth_reduction( * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly * 1: YCbCr 4:2:2 */ -static void set_pixel_encoding( +static void opp1_set_pixel_encoding( struct dcn10_opp *oppn10, const struct clamping_and_pixel_encoding_params *params) { @@ -186,7 +204,7 @@ static void set_pixel_encoding( * 7 for programable * 2) Enable clamp if Limited range requested */ -static void opp_set_clamping( +static void opp1_set_clamping( struct dcn10_opp *oppn10, const struct clamping_and_pixel_encoding_params *params) { @@ -224,7 +242,7 @@ static void opp_set_clamping( } -static void oppn10_set_dyn_expansion( +static void opp1_set_dyn_expansion( struct output_pixel_processor *opp, enum dc_color_space color_sp, enum dc_color_depth color_dpth, @@ -264,17 +282,17 @@ static void oppn10_set_dyn_expansion( } } -static void opp_program_clamping_and_pixel_encoding( +static void opp1_program_clamping_and_pixel_encoding( struct output_pixel_processor *opp, const struct clamping_and_pixel_encoding_params *params) { struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - opp_set_clamping(oppn10, params); - set_pixel_encoding(oppn10, params); + opp1_set_clamping(oppn10, params); + opp1_set_pixel_encoding(oppn10, params); } -static void oppn10_program_fmt( +static void opp1_program_fmt( struct output_pixel_processor *opp, struct bit_depth_reduction_params *fmt_bit_depth, struct clamping_and_pixel_encoding_params *clamping) @@ -286,20 +304,18 @@ static void oppn10_program_fmt( /* dithering is affected by , hence should be * programmed afterwards */ - oppn10_program_bit_depth_reduction( + opp1_program_bit_depth_reduction( opp, fmt_bit_depth); - opp_program_clamping_and_pixel_encoding( + opp1_program_clamping_and_pixel_encoding( opp, clamping); return; } - - -static void oppn10_set_stereo_polarity( +static void opp1_set_stereo_polarity( struct output_pixel_processor *opp, bool enable, bool rightEyePolarity) { @@ -312,18 +328,18 @@ static void oppn10_set_stereo_polarity( /* Constructor, Destructor */ /*****************************************/ -static void dcn10_opp_destroy(struct output_pixel_processor **opp) +static void opp1_destroy(struct output_pixel_processor **opp) { kfree(TO_DCN10_OPP(*opp)); *opp = NULL; } static struct opp_funcs dcn10_opp_funcs = { - .opp_set_dyn_expansion = oppn10_set_dyn_expansion, - .opp_program_fmt = oppn10_program_fmt, - .opp_program_bit_depth_reduction = oppn10_program_bit_depth_reduction, - .opp_set_stereo_polarity = oppn10_set_stereo_polarity, - .opp_destroy = dcn10_opp_destroy + .opp_set_dyn_expansion = opp1_set_dyn_expansion, + .opp_program_fmt = opp1_program_fmt, + .opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction, + .opp_set_stereo_polarity = opp1_set_stereo_polarity, + .opp_destroy = opp1_destroy }; void dcn10_opp_construct(struct dcn10_opp *oppn10, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h index 790ce60..cdb220e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h @@ -78,36 +78,14 @@ type DPG_MODE; \ type DPG_VRES; \ type DPG_HRES; \ + type DPG_ACTIVE_WIDTH; \ + type DPG_ACTIVE_HEIGHT; \ type DPG_COLOUR0_R_CR; \ type DPG_COLOUR1_R_CR; \ type DPG_COLOUR0_B_CB; \ type DPG_COLOUR1_B_CB; \ type DPG_COLOUR0_G_Y; \ type DPG_COLOUR1_G_Y; \ - type CM_OCSC_C11; \ - type CM_OCSC_C12; \ - type CM_OCSC_C13; \ - type CM_OCSC_C14; \ - type CM_OCSC_C21; \ - type CM_OCSC_C22; \ - type CM_OCSC_C23; \ - type CM_OCSC_C24; \ - type CM_OCSC_C31; \ - type CM_OCSC_C32; \ - type CM_OCSC_C33; \ - type CM_OCSC_C34; \ - type CM_COMB_C11; \ - type CM_COMB_C12; \ - type CM_COMB_C13; \ - type CM_COMB_C14; \ - type CM_COMB_C21; \ - type CM_COMB_C22; \ - type CM_COMB_C23; \ - type CM_COMB_C24; \ - type CM_COMB_C31; \ - type CM_COMB_C32; \ - type CM_COMB_C33; \ - type CM_COMB_C34; \ type FMT_TRUNCATE_EN; \ type FMT_TRUNCATE_DEPTH; \ type FMT_TRUNCATE_MODE; \ @@ -129,33 +107,22 @@ type FMT_DYNAMIC_EXP_EN; \ type FMT_DYNAMIC_EXP_MODE; \ type FMT_MAP420MEM_PWR_FORCE; \ - type FMT_STEREOSYNC_OVERRIDE + type FMT_STEREOSYNC_OVERRIDE; struct dcn10_opp_shift { - OPP_DCN10_REG_FIELD_LIST(uint8_t); + OPP_DCN10_REG_FIELD_LIST(uint8_t) }; struct dcn10_opp_mask { - OPP_DCN10_REG_FIELD_LIST(uint32_t); + OPP_DCN10_REG_FIELD_LIST(uint32_t) }; struct dcn10_opp_registers { uint32_t DPG_CONTROL; + uint32_t DPG_DIMENSIONS; uint32_t DPG_COLOUR_B_CB; uint32_t DPG_COLOUR_G_Y; uint32_t DPG_COLOUR_R_CR; - uint32_t CM_OCSC_C11_C12; - uint32_t CM_OCSC_C13_C14; - uint32_t CM_OCSC_C21_C22; - uint32_t CM_OCSC_C23_C24; - uint32_t CM_OCSC_C31_C32; - uint32_t CM_OCSC_C33_C34; - uint32_t CM_COMB_C11_C12; - uint32_t CM_COMB_C13_C14; - uint32_t CM_COMB_C21_C22; - uint32_t CM_COMB_C23_C24; - uint32_t CM_COMB_C31_C32; - uint32_t CM_COMB_C33_C34; uint32_t FMT_BIT_DEPTH_CONTROL; uint32_t FMT_CONTROL; uint32_t FMT_DITHER_RAND_R_SEED; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 75adb8f..8141b67 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -284,6 +284,12 @@ struct opp_funcs { void (*opp_set_test_pattern)( struct output_pixel_processor *opp, bool enable); + + void (*opp_dpg_blank_enable)( + struct output_pixel_processor *opp, + bool enable, + int width, + int height); }; #endif -- 2.7.4