From 85546a89affd431419b66e1cf9f185a4992da632 Mon Sep 17 00:00:00 2001 From: "Le.Ma" Date: Mon, 4 Dec 2017 17:42:04 +0800 Subject: [PATCH 2678/4131] drm/amd/display: Fix wrongly deleted useful code This patch fix previous wrongly deleted code in patch below: "drm/amd/display: fix HDMI 12bits last two bits are zero issue" Change-Id: I6a1f7caed07f110ced72a24feacfde13c35d3d46 Signed-off-by: Le.Ma --- .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 1f47f1b..a93513f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1298,14 +1298,14 @@ static enum dc_status apply_single_controller_ctx_to_hw( /* */ dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc); - pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( - pipe_ctx->stream_res.opp, - COLOR_SPACE_YCBCR601, - stream->timing.display_color_depth, - pipe_ctx->stream->signal); - /* FPGA does not program backend */ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( + pipe_ctx->stream_res.opp, + COLOR_SPACE_YCBCR601, + stream->timing.display_color_depth, + pipe_ctx->stream->signal); + pipe_ctx->stream_res.opp->funcs->opp_program_fmt( pipe_ctx->stream_res.opp, &stream->bit_depth_params, @@ -1318,6 +1318,11 @@ static enum dc_status apply_single_controller_ctx_to_hw( BREAK_TO_DEBUGGER(); return DC_ERROR_UNEXPECTED; } + pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( + pipe_ctx->stream_res.opp, + COLOR_SPACE_YCBCR601, + stream->timing.display_color_depth, + pipe_ctx->stream->signal); if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) stream->sink->link->link_enc->funcs->setup( -- 2.7.4