From b3d5a15199a5d602ac05fa72436368f5337fff15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 18 Sep 2017 13:58:30 +0200 Subject: [PATCH 1967/4131] drm/amdgpu: add VM support for huge pages v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert GTT mappings into linear ones for huge page handling. v2: use fragment size as minimum for linear conversion Some conflicts are fixed when cherry-pick this patch to dkms-4.13 branch. Change-Id: I2a201995cdaa730bd2e648079d2a2f70c32be635 Signed-off-by: Christian König Reviewed-by: Felix Kuehling Acked-by: Alex Deucher Signed-off-by: Roger He Reviewed-by: Le.Ma --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 8517a6b..7c7020d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1709,6 +1709,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, struct dma_fence **fence) { struct drm_mm_node *nodes = mem ? mem->mm_node : NULL; + unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size; uint64_t pfn, start = mapping->start; int r; @@ -1743,8 +1744,10 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, } do { + dma_addr_t *dma_addr = NULL; uint64_t max_entries; uint64_t addr, last; + uint64_t count; if (nodes) { addr = nodes->start << PAGE_SHIFT; @@ -1753,19 +1756,37 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, switch (mem->mem_type) { case TTM_PL_TT: max_entries = min(max_entries, 16ull * 1024ull); - addr = 0; + + for (count = 1; count < max_entries; ++count) { + uint64_t idx = pfn + count; + + if (pages_addr[idx] != + (pages_addr[idx - 1] + PAGE_SIZE)) + break; + } + + if (count < min_linear_pages) { + addr = pfn << PAGE_SHIFT; + dma_addr = pages_addr; + } else { + addr = pages_addr[pfn]; + max_entries = count; + } break; case AMDGPU_PL_DGMA_IMPORT: addr = 0; max_entries = min(max_entries, 16ull * 1024ull); + dma_addr = pages_addr; break; case AMDGPU_PL_DGMA: addr += adev->vm_manager.vram_base_offset + adev->mman.bdev.man[mem->mem_type].gpu_offset - adev->mman.bdev.man[TTM_PL_VRAM].gpu_offset; + addr += pfn << PAGE_SHIFT; break; case TTM_PL_VRAM: addr += adev->vm_manager.vram_base_offset; + addr += pfn << PAGE_SHIFT; break; default: break; @@ -1775,10 +1796,8 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, max_entries = S64_MAX; } - addr += pfn << PAGE_SHIFT; - last = min((uint64_t)mapping->last, start + max_entries - 1); - r = amdgpu_vm_bo_update_mapping(adev, exclusive, pages_addr, vm, + r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm, start, last, flags, addr, fence); if (r) -- 2.7.4