From f3f39aa50d8a7ac4d9d466df131fe3818e891888 Mon Sep 17 00:00:00 2001 From: Ken Wang Date: Fri, 29 Sep 2017 15:41:43 +0800 Subject: [PATCH 1824/4131] drm/amdgpu: correct reference clock value on vega10 Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474 Signed-off-by: Ken Wang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index f0c9904..98acd31 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -279,7 +279,10 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev) } static u32 soc15_get_xclk(struct amdgpu_device *adev) { - return adev->clock.spll.reference_freq; + if (adev->asic_type == CHIP_VEGA10) + return 27000; + else + return adev->clock.spll.reference_freq; } -- 2.7.4