From faa173b810cdfd138ac02fd912f17cf99c492f33 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Thu, 3 Aug 2017 08:59:12 -0400 Subject: [PATCH 0734/4131] drm/amd/display: log HW state when we about to encounter DF DPM hang Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 115 +++++++++++---------- 1 file changed, 58 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e698398..30ddf92 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -52,6 +52,61 @@ #define FN(reg_name, field_name) \ hws->shifts->field_name, hws->masks->field_name +static void log_mpc_crc(struct core_dc *dc) +{ + struct dc_context *dc_ctx = dc->ctx; + struct dce_hwseq *hws = dc->hwseq; + + if (REG(MPC_CRC_RESULT_GB)) + DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n", + REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR)); + if (REG(DPP_TOP0_DPP_CRC_VAL_B_A)) + DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n", + REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G)); +} + +static void dcn10_log_hw_state(struct core_dc *dc) +{ + struct dc_context *dc_ctx = dc->ctx; + struct resource_pool *pool = dc->res_pool; + int i; + + DTN_INFO_BEGIN(); + + DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t rotation \t" + "mirror \t sw_mode \t dcc_en \t blank_en \t ttu_dis \t" + "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n"); + + for (i = 0; i < pool->pipe_count; i++) { + struct mem_input *mi = pool->mis[i]; + struct dcn_hubp_state s; + + dcn10_mem_input_read_state(TO_DCN10_MEM_INPUT(mi), &s); + + DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t %xh \t %xh \t " + "%d \t %d \t %d \t %d \t" + "%d \t %d \t %d \n", + i, + s.pixel_format, + s.inuse_addr_hi, + s.viewport_width, + s.viewport_height, + s.rotation_angle, + s.h_mirror_en, + s.sw_mode, + s.dcc_en, + s.blank_en, + s.ttu_disable, + s.min_ttu_vblank, + s.qos_level_low_wm, + s.qos_level_high_wm); + } + DTN_INFO("\n"); + + log_mpc_crc(dc); + + DTN_INFO_END(); +} static void verify_allow_pstate_change_high( struct dce_hwseq *hws) @@ -118,6 +173,9 @@ static void verify_allow_pstate_change_high( */ REG_WRITE(DCHUBBUB_ARB_DRAM_STATE_CNTL, force_allow_pstate); forced_pstate_allow = true; + + dcn10_log_hw_state(DC_TO_CORE(hws->ctx->dc)); + BREAK_TO_DEBUGGER(); } @@ -2377,63 +2435,6 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) return; } - -static void log_mpc_crc(struct core_dc *dc) -{ - struct dc_context *dc_ctx = dc->ctx; - struct dce_hwseq *hws = dc->hwseq; - - if (REG(MPC_CRC_RESULT_GB)) - DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n", - REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR)); - if (REG(DPP_TOP0_DPP_CRC_VAL_B_A)) - DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n", - REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G)); -} - -static void dcn10_log_hw_state(struct core_dc *dc) -{ - struct dc_context *dc_ctx = dc->ctx; - struct resource_pool *pool = dc->res_pool; - int i; - - DTN_INFO_BEGIN(); - - DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t rotation \t" - "mirror \t sw_mode \t dcc_en \t blank_en \t ttu_dis \t" - "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n"); - - for (i = 0; i < pool->pipe_count; i++) { - struct mem_input *mi = pool->mis[i]; - struct dcn_hubp_state s; - - dcn10_mem_input_read_state(TO_DCN10_MEM_INPUT(mi), &s); - - DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t %xh \t %xh \t " - "%d \t %d \t %d \t %d \t" - "%d \t %d \t %d \n", - i, - s.pixel_format, - s.inuse_addr_hi, - s.viewport_width, - s.viewport_height, - s.rotation_angle, - s.h_mirror_en, - s.sw_mode, - s.dcc_en, - s.blank_en, - s.ttu_disable, - s.min_ttu_vblank, - s.qos_level_low_wm, - s.qos_level_high_wm); - } - DTN_INFO("\n"); - - log_mpc_crc(dc); - - DTN_INFO_END(); -} - static void dcn10_wait_for_mpcc_disconnect( struct core_dc *dc, struct resource_pool *res_pool, -- 2.7.4