From 184b7565c49ef67b31fabdf5236a7dad495e35f9 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Fri, 28 Jul 2017 14:16:13 -0400 Subject: [PATCH 0701/4131] drm/amd/display: fix dcn fe reset memory access error Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e1298d7..fa19c6b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -853,8 +853,9 @@ static void plane_atomic_disable(struct core_dc *dc, struct dce_hwseq *hws = dc->hwseq; struct mem_input *mi = dc->res_pool->mis[fe_idx]; struct mpc *mpc = dc->res_pool->mpc; + int opp_id = mi->opp_id; - if (mi->opp_id == 0xf) + if (opp_id == 0xf) return; mpc->funcs->wait_for_idle(mpc, mi->mpcc_id); @@ -876,8 +877,8 @@ static void plane_atomic_disable(struct core_dc *dc, REG_UPDATE(DPP_CONTROL[fe_idx], DPP_CLOCK_ENABLE, 0); - if (dc->res_pool->opps[mi->opp_id]->mpc_tree.num_pipes == 0) - REG_UPDATE(OPP_PIPE_CONTROL[mi->opp_id], + if (dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0) + REG_UPDATE(OPP_PIPE_CONTROL[opp_id], OPP_PIPE_CLOCK_EN, 0); if (dc->public.debug.sanity_checks) -- 2.7.4