From 0df37abc2b52e4962515c38fb9b1cfd5dfd7974e Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 9 Jun 2017 10:12:36 -0400 Subject: [PATCH 0522/4131] drm/amd/display: Don't call DCN clk code for Vega Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 10 ++++++---- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 84b0860..4e3f4e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -614,11 +614,13 @@ static bool dce_apply_clock_voltage_request( } if (send_request) { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); - /*use dcfclk request voltage*/ - clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; - clock_voltage_req.clocks_in_khz = + if (clk->ctx->dce_version == DCN_VERSION_1_0) { + struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); + /*use dcfclk request voltage*/ + clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; + clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(core_dc, &clk->cur_clocks_value); + } #endif dm_pp_apply_clock_for_voltage_request( clk->ctx, &clock_voltage_req); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index ac99d28..7c50981 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1633,7 +1633,7 @@ enum dc_status dce110_apply_ctx_to_hw( apply_min_clocks(dc, context, &clocks_state, true); #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (resource_parse_asic_id(dc->ctx->asic_id) == DCN_VERSION_1_0) { + if (dc->ctx->dce_version == DCN_VERSION_1_0) { if (context->bw.dcn.calc_clk.fclk_khz > dc->current_context->bw.dcn.cur_clk.fclk_khz) { struct dm_pp_clock_for_voltage_req clock; -- 2.7.4