From 580e3097256af8b3e0c0bd09e06a708364bd3927 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Thu, 8 Jun 2017 14:26:40 -0400 Subject: [PATCH 0511/4131] drm/amd/display: disable dcc when reset front end. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 15 +++++++++++---- drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 3 +++ 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 93a34e2..f2b581f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -825,6 +825,8 @@ static void reset_front_end_for_pipe( if (!pipe_ctx->surface) return; + pipe_ctx->mi->funcs->dcc_control(pipe_ctx->mi, false, false); + lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst); /* TODO: build stream pipes group id. For now, use stream otg diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c index 8ad7062..a58993a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c @@ -369,16 +369,22 @@ static bool mem_input_program_surface_flip_and_addr( return true; } -static void program_control(struct dcn10_mem_input *mi, - struct dc_plane_dcc_param *dcc) +static void dcc_control(struct mem_input *mem_input, bool enable, + bool independent_64b_blks) { - uint32_t dcc_en = dcc->enable ? 1 : 0; - uint32_t dcc_ind_64b_blk = dcc->grph.independent_64b_blks ? 1 : 0; + uint32_t dcc_en = enable ? 1 : 0; + uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; + struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); REG_UPDATE_2(DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, dcc_en, PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); +} +static void program_control(struct dcn10_mem_input *mi, + struct dc_plane_dcc_param *dcc) +{ + dcc_control(&mi->base, dcc->enable, dcc->grph.independent_64b_blks); } static void mem_input_program_surface_config( @@ -1072,6 +1078,7 @@ static struct mem_input_funcs dcn10_mem_input_funcs = { .mem_input_update_dchub = mem_input_update_dchub, .mem_input_program_pte_vm = dcn_mem_input_program_pte_vm, .set_blank = dcn_mi_set_blank, + .dcc_control = dcc_control, }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index bd0dfeb..64b810d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -86,6 +86,9 @@ struct mem_input_funcs { struct _vcs_dpi_display_ttu_regs_st *ttu_regs, struct _vcs_dpi_display_rq_regs_st *rq_regs, struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); + + void (*dcc_control)(struct mem_input *mem_input, bool enable, + bool independent_64b_blks); #endif void (*mem_input_program_display_marks)( -- 2.7.4