From 3eeb98ed4758eea0a220937fae26f7eaae015fff Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 20 Dec 2019 14:53:35 -0500 Subject: [PATCH 1155/1453] drm/amdgpu/smu/navi: Adjust default behavior for peak sclk profile Fetch the sclk from the pptable if there is no specified sclk for the board. Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index bf87e93b26fc..c33744a0d46b 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -1587,7 +1587,7 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu) struct amdgpu_device *adev = smu->adev; int ret = 0; uint32_t sclk_freq = 0, uclk_freq = 0; - uint32_t uclk_level = 0; + uint32_t sclk_level = 0, uclk_level = 0; switch (adev->asic_type) { case CHIP_NAVI10: @@ -1629,7 +1629,13 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu) } break; default: - return -EINVAL; + ret = smu_get_dpm_level_count(smu, SMU_SCLK, &sclk_level); + if (ret) + return ret; + ret = smu_get_dpm_freq_by_index(smu, SMU_SCLK, sclk_level - 1, &sclk_freq); + if (ret) + return ret; + break; } ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level); -- 2.17.1