From patchwork Fri Mar 9 08:35:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [dpdk-dev,v4,03/20] crypto/ccp: support basic pmd ops From: Ravi Kumar X-Patchwork-Id: 35802 X-Patchwork-Delegate: pablo.de.lara.guarch@intel.com Message-Id: <1520584520-130522-3-git-send-email-Ravi1.kumar@amd.com> List-Id: dev.dpdk.org To: dev@dpdk.org Cc: pablo.de.lara.guarch@intel.com Date: Fri, 9 Mar 2018 03:35:03 -0500 Signed-off-by: Ravi Kumar --- drivers/crypto/ccp/ccp_dev.c | 9 ++++++ drivers/crypto/ccp/ccp_dev.h | 9 ++++++ drivers/crypto/ccp/ccp_pmd_ops.c | 61 +++++++++++++++++++++++++++++++++--- drivers/crypto/ccp/ccp_pmd_private.h | 43 +++++++++++++++++++++++++ 4 files changed, 117 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/ccp/ccp_dev.c b/drivers/crypto/ccp/ccp_dev.c index 5af2b49..57bccf4 100644 --- a/drivers/crypto/ccp/ccp_dev.c +++ b/drivers/crypto/ccp/ccp_dev.c @@ -52,6 +52,15 @@ struct ccp_list ccp_list = TAILQ_HEAD_INITIALIZER(ccp_list); static int ccp_dev_id; +int +ccp_dev_start(struct rte_cryptodev *dev) +{ + struct ccp_private *priv = dev->data->dev_private; + + priv->last_dev = TAILQ_FIRST(&ccp_list); + return 0; +} + static const struct rte_memzone * ccp_queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size, diff --git a/drivers/crypto/ccp/ccp_dev.h b/drivers/crypto/ccp/ccp_dev.h index fe05bf0..b321530 100644 --- a/drivers/crypto/ccp/ccp_dev.h +++ b/drivers/crypto/ccp/ccp_dev.h @@ -104,6 +104,10 @@ #define LSB_ITEM_SIZE 32 #define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE) +/* General CCP Defines */ + +#define CCP_SB_BYTES 32 + /* bitmap */ enum { BITS_PER_WORD = sizeof(unsigned long) * CHAR_BIT @@ -299,6 +303,11 @@ high32_value(unsigned long addr) return ((uint64_t)addr >> 32) & 0x00000ffff; } +/* + * Start CCP device + */ +int ccp_dev_start(struct rte_cryptodev *dev); + /** * Detect ccp platform and initialize all ccp devices * diff --git a/drivers/crypto/ccp/ccp_pmd_ops.c b/drivers/crypto/ccp/ccp_pmd_ops.c index bc4120b..b6f8c48 100644 --- a/drivers/crypto/ccp/ccp_pmd_ops.c +++ b/drivers/crypto/ccp/ccp_pmd_ops.c @@ -28,18 +28,69 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include + +#include #include +#include + +#include "ccp_pmd_private.h" +#include "ccp_dev.h" + +static const struct rte_cryptodev_capabilities ccp_pmd_capabilities[] = { + RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() +}; + +static int +ccp_pmd_config(struct rte_cryptodev *dev __rte_unused, + struct rte_cryptodev_config *config __rte_unused) +{ + return 0; +} + +static int +ccp_pmd_start(struct rte_cryptodev *dev) +{ + return ccp_dev_start(dev); +} + +static void +ccp_pmd_stop(struct rte_cryptodev *dev __rte_unused) +{ + +} + +static int +ccp_pmd_close(struct rte_cryptodev *dev __rte_unused) +{ + return 0; +} + +static void +ccp_pmd_info_get(struct rte_cryptodev *dev, + struct rte_cryptodev_info *dev_info) +{ + struct ccp_private *internals = dev->data->dev_private; + + if (dev_info != NULL) { + dev_info->driver_id = dev->driver_id; + dev_info->feature_flags = dev->feature_flags; + dev_info->capabilities = ccp_pmd_capabilities; + dev_info->max_nb_queue_pairs = internals->max_nb_qpairs; + dev_info->sym.max_nb_sessions = internals->max_nb_sessions; + } +} struct rte_cryptodev_ops ccp_ops = { - .dev_configure = NULL, - .dev_start = NULL, - .dev_stop = NULL, - .dev_close = NULL, + .dev_configure = ccp_pmd_config, + .dev_start = ccp_pmd_start, + .dev_stop = ccp_pmd_stop, + .dev_close = ccp_pmd_close, .stats_get = NULL, .stats_reset = NULL, - .dev_infos_get = NULL, + .dev_infos_get = ccp_pmd_info_get, .queue_pair_setup = NULL, .queue_pair_release = NULL, diff --git a/drivers/crypto/ccp/ccp_pmd_private.h b/drivers/crypto/ccp/ccp_pmd_private.h index f5b6061..d278a8c 100644 --- a/drivers/crypto/ccp/ccp_pmd_private.h +++ b/drivers/crypto/ccp/ccp_pmd_private.h @@ -60,13 +60,56 @@ #define CCP_NB_MAX_DESCRIPTORS 1024 #define CCP_MAX_BURST 64 +#include "ccp_dev.h" + /* private data structure for each CCP crypto device */ struct ccp_private { unsigned int max_nb_qpairs; /**< Max number of queue pairs */ unsigned int max_nb_sessions; /**< Max number of sessions */ uint8_t crypto_num_dev; /**< Number of working crypto devices */ + struct ccp_device *last_dev; /**< Last working crypto device */ }; +/* CCP batch info */ +struct ccp_batch_info { + struct rte_crypto_op *op[CCP_MAX_BURST]; + /**< optable populated at enque time from app*/ + int op_idx; + struct ccp_queue *cmd_q; + uint16_t opcnt; + /**< no. of crypto ops in batch*/ + int desccnt; + /**< no. of ccp queue descriptors*/ + uint32_t head_offset; + /**< ccp queue head tail offsets time of enqueue*/ + uint32_t tail_offset; + uint8_t lsb_buf[CCP_SB_BYTES * CCP_MAX_BURST]; + phys_addr_t lsb_buf_phys; + /**< LSB intermediate buf for passthru */ + int lsb_buf_idx; +} __rte_cache_aligned; + +/**< CCP crypto queue pair */ +struct ccp_qp { + uint16_t id; + /**< Queue Pair Identifier */ + char name[RTE_CRYPTODEV_NAME_MAX_LEN]; + /**< Unique Queue Pair Name */ + struct rte_ring *processed_pkts; + /**< Ring for placing process packets */ + struct rte_mempool *sess_mp; + /**< Session Mempool */ + struct rte_mempool *batch_mp; + /**< Session Mempool for batch info */ + struct rte_cryptodev_stats qp_stats; + /**< Queue pair statistics */ + struct ccp_batch_info *b_info; + /**< Store ops pulled out of queue */ + struct rte_cryptodev *dev; + /**< rte crypto device to which this qp belongs */ +} __rte_cache_aligned; + + /**< device specific operations function pointer structure */ extern struct rte_cryptodev_ops *ccp_pmd_ops;