diff options
Diffstat (limited to 'meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch')
| -rw-r--r-- | meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch b/meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch index 529fee1d..d589b7d5 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch @@ -6,6 +6,7 @@ Subject: [PATCH 20/39] amdgpu: implement direct gma Change-Id: I37a6a0f79a91b8e793fc90eb3955045bebf24848 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu.h | 43 +++++++++++++++++++++++++++++++++++++ amdgpu/amdgpu_bo.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++- @@ -13,10 +14,10 @@ Signed-off-by: Avinash M N <avimn@amd.com> 3 files changed, 109 insertions(+), 1 deletion(-) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 38b3597..e7a566f 100644 +index f2baa26..423ad28 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -731,6 +731,49 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, +@@ -736,6 +736,49 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, amdgpu_bo_handle *buf_handle, uint64_t *offset_in_bo); @@ -47,8 +48,8 @@ index 38b3597..e7a566f 100644 + * It is responsibility of caller to correctly specify physical_address +*/ +int amdgpu_create_bo_from_phys_mem(amdgpu_device_handle dev, -+ uint64_t phys_address, uint64_t size, -+ amdgpu_bo_handle *buf_handle); ++ uint64_t phys_address, uint64_t size, ++ amdgpu_bo_handle *buf_handle); + +/** + * Get physical address from BO @@ -62,25 +63,25 @@ index 38b3597..e7a566f 100644 + * +*/ +int amdgpu_bo_get_phys_address(amdgpu_bo_handle buf_handle, -+ uint64_t *phys_address); ++ uint64_t *phys_address); /** * Free previosuly allocated memory diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index fef6152..5a9cdbe2 100644 +index 8737d51..8f32d8d 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c -@@ -87,7 +87,8 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev, +@@ -60,7 +60,8 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev, int r = 0; /* It's an error if the heap is not specified */ - if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM))) + if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM -+ | AMDGPU_GEM_DOMAIN_DGMA))) ++ | AMDGPU_GEM_DOMAIN_DGMA))) return -EINVAL; bo = calloc(1, sizeof(struct amdgpu_bo)); -@@ -570,6 +571,58 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc +@@ -544,6 +545,58 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc return r; } @@ -138,28 +139,28 @@ index fef6152..5a9cdbe2 100644 + int amdgpu_bo_free(amdgpu_bo_handle buf_handle) { - /* Just drop the reference. */ + struct amdgpu_device *dev; diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index bd34a86..b515809 100644 +index 0598a47..088cb3f 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -53,6 +53,7 @@ extern "C" { - #define DRM_AMDGPU_WAIT_FENCES 0x12 - #define DRM_AMDGPU_VM 0x13 +@@ -55,6 +55,7 @@ extern "C" { + #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 + #define DRM_AMDGPU_SCHED 0x15 /* hybrid specific ioctls */ -+#define DRM_AMDGPU_GEM_DGMA 0x5c - #define DRM_AMDGPU_FREESYNC 0x5d ++#define DRM_AMDGPU_GEM_DGMA 0x5c + #define DRM_AMDGPU_FREESYNC 0x5d #define DRM_AMDGPU_GEM_FIND_BO 0x5f -@@ -71,6 +72,7 @@ extern "C" { - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) +@@ -75,6 +76,7 @@ extern "C" { + #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) + #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) /* hybrid specific ioctls */ -+#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) ++#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) - #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) + #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) -@@ -80,6 +82,7 @@ extern "C" { +@@ -84,6 +86,7 @@ extern "C" { #define AMDGPU_GEM_DOMAIN_GDS 0x8 #define AMDGPU_GEM_DOMAIN_GWS 0x10 #define AMDGPU_GEM_DOMAIN_OA 0x20 @@ -167,17 +168,17 @@ index bd34a86..b515809 100644 /* Flag that CPU access will be required for the case of VRAM domain */ #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) -@@ -243,6 +246,15 @@ struct drm_amdgpu_gem_userptr { +@@ -283,6 +286,15 @@ struct drm_amdgpu_gem_userptr { __u32 handle; }; -+#define AMDGPU_GEM_DGMA_IMPORT 0 -+#define AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR 1 ++#define AMDGPU_GEM_DGMA_IMPORT 0 ++#define AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR 1 +struct drm_amdgpu_gem_dgma { -+ uint64_t addr; -+ uint64_t size; -+ uint32_t op; -+ uint32_t handle; ++ uint64_t addr; ++ uint64_t size; ++ uint32_t op; ++ uint32_t handle; +}; + struct drm_amdgpu_gem_find_bo { @@ -185,4 +186,3 @@ index bd34a86..b515809 100644 uint64_t size; -- 2.7.4 - |