diff options
Diffstat (limited to 'meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5559-drm-amdgpu-vcn-Add-DPG-mode-Register-XX-check.patch')
| -rw-r--r-- | meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5559-drm-amdgpu-vcn-Add-DPG-mode-Register-XX-check.patch | 43 |
1 files changed, 0 insertions, 43 deletions
diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5559-drm-amdgpu-vcn-Add-DPG-mode-Register-XX-check.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5559-drm-amdgpu-vcn-Add-DPG-mode-Register-XX-check.patch deleted file mode 100644 index ec9bfeb6..00000000 --- a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5559-drm-amdgpu-vcn-Add-DPG-mode-Register-XX-check.patch +++ /dev/null @@ -1,43 +0,0 @@ -From bc096e2aedaf0ced0b8371d217541c757701b74e Mon Sep 17 00:00:00 2001 -From: James Zhu <James.Zhu@amd.com> -Date: Thu, 4 Oct 2018 16:02:51 -0400 -Subject: [PATCH 5559/5725] drm/amdgpu/vcn:Add DPG mode Register XX check - -Add Dynamic Power Gate mode Register XX check - -Signed-off-by: James Zhu <James.Zhu@amd.com> -Acked-by: Leo Liu <leo.liu@amd.com> -Acked-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c -index 10e0b19..86bb57c 100644 ---- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c -@@ -37,6 +37,11 @@ - - #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" - -+#define mmUVD_RBC_XX_IB_REG_CHECK 0x05ab -+#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1 -+#define mmUVD_REG_XX_MASK 0x05ac -+#define mmUVD_REG_XX_MASK_BASE_IDX 1 -+ - static int vcn_v1_0_stop(struct amdgpu_device *adev); - static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); - static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); -@@ -1031,6 +1036,9 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) - - vcn_v1_0_mc_resume_dpg_mode(adev); - -+ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); -+ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); -+ - /* take all subblocks out of reset, except VCPU */ - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, - UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0xFFFFFFFF, 0); --- -2.7.4 - |