diff options
Diffstat (limited to 'meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5266-drm-amdgpu-add-clockgating-support-for-picasso.patch')
| -rw-r--r-- | meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5266-drm-amdgpu-add-clockgating-support-for-picasso.patch | 73 |
1 files changed, 0 insertions, 73 deletions
diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5266-drm-amdgpu-add-clockgating-support-for-picasso.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5266-drm-amdgpu-add-clockgating-support-for-picasso.patch deleted file mode 100644 index 8031e760..00000000 --- a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5266-drm-amdgpu-add-clockgating-support-for-picasso.patch +++ /dev/null @@ -1,73 +0,0 @@ -From a83a269a4d973a5b2c22a8f0e04e0a91d56d818c Mon Sep 17 00:00:00 2001 -From: Likun Gao <Likun.Gao@amd.com> -Date: Tue, 10 Jul 2018 20:25:24 +0800 -Subject: [PATCH 5266/5725] drm/amdgpu: add clockgating support for picasso - -Treat it the same as raven for now. - -Signed-off-by: Likun Gao <Likun.Gao@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Reviewed-by: Huang Rui <ray.huang@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c -index 5f6a9c8..8875e10 100644 ---- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c -@@ -614,7 +614,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad - - def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); - -- if (adev->asic_type != CHIP_RAVEN) { -+ if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) { - def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); - def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); - } else -@@ -630,7 +630,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad - DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | - DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); - -- if (adev->asic_type != CHIP_RAVEN) -+ if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) - data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | -@@ -647,7 +647,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad - DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | - DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); - -- if (adev->asic_type != CHIP_RAVEN) -+ if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) - data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | -@@ -660,13 +660,13 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad - WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); - - if (def1 != data1) { -- if (adev->asic_type != CHIP_RAVEN) -+ if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) - WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); - else - WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); - } - -- if (adev->asic_type != CHIP_RAVEN && def2 != data2) -+ if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO && def2 != data2) - WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); - } - -@@ -730,6 +730,7 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, - case CHIP_VEGA12: - case CHIP_VEGA20: - case CHIP_RAVEN: -+ case CHIP_PICASSO: - mmhub_v1_0_update_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); - athub_update_medium_grain_clock_gating(adev, --- -2.7.4 - |