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Diffstat (limited to 'meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5138-drm-amd-powerplay-update-vega20-clocks-threshold-set.patch')
-rw-r--r--meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5138-drm-amd-powerplay-update-vega20-clocks-threshold-set.patch159
1 files changed, 0 insertions, 159 deletions
diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5138-drm-amd-powerplay-update-vega20-clocks-threshold-set.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5138-drm-amd-powerplay-update-vega20-clocks-threshold-set.patch
deleted file mode 100644
index 78c4442e..00000000
--- a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5138-drm-amd-powerplay-update-vega20-clocks-threshold-set.patch
+++ /dev/null
@@ -1,159 +0,0 @@
-From a153848ba79cc69ea6ff454678f8f7337c338def Mon Sep 17 00:00:00 2001
-From: Evan Quan <evan.quan@amd.com>
-Date: Mon, 21 May 2018 10:43:31 +0800
-Subject: [PATCH 5138/5725] drm/amd/powerplay: update vega20 clocks threshold
- settings on power state adjust
-
-UVD, VCE and SOC clocks need to be taken into consideration. Also, the
-thresholds need be updated correspondingly when stable power state is selected.
-
-Signed-off-by: Evan Quan <evan.quan@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 112 +++++++++++++++++++++
- 1 file changed, 112 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
-index 3f769f3..ed928c5 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
-@@ -2503,6 +2503,23 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
- dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
- dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-
-+ if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
-+ if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
-+ }
-+
-+ if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
-+ }
-+
-+ if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ }
-+ }
-+
- /* memclk */
- dpm_table = &(data->dpm_table.mem_table);
- dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
-@@ -2510,9 +2527,28 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
- dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
- dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-
-+ if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
-+ if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
-+ }
-+
-+ if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
-+ }
-+
-+ if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ }
-+ }
-+
-+ /* honour DAL's UCLK Hardmin */
- if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
- dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
-
-+ /* Hardmin is dependent on displayconfig */
- if (disable_mclk_switching) {
- dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
- for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
-@@ -2528,6 +2564,82 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
- if (hwmgr->display_config->nb_pstate_switch_disable)
- dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-
-+ /* vclk */
-+ dpm_table = &(data->dpm_table.vclk_table);
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
-+ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+
-+ if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
-+ if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
-+ }
-+
-+ if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ }
-+ }
-+
-+ /* dclk */
-+ dpm_table = &(data->dpm_table.dclk_table);
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
-+ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+
-+ if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
-+ if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
-+ }
-+
-+ if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ }
-+ }
-+
-+ /* socclk */
-+ dpm_table = &(data->dpm_table.soc_table);
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
-+ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+
-+ if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
-+ if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
-+ }
-+
-+ if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ }
-+ }
-+
-+ /* eclk */
-+ dpm_table = &(data->dpm_table.eclk_table);
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
-+ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+
-+ if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
-+ if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
-+ }
-+
-+ if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
-+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
-+ }
-+ }
-+
- return 0;
- }
-
---
-2.7.4
-
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-06-07 11:19:52 +0000