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Diffstat (limited to 'meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4752-drm-amd-display-replace-clocks_value-struct-with-dc_.patch')
-rw-r--r--meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4752-drm-amd-display-replace-clocks_value-struct-with-dc_.patch378
1 files changed, 0 insertions, 378 deletions
diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4752-drm-amd-display-replace-clocks_value-struct-with-dc_.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4752-drm-amd-display-replace-clocks_value-struct-with-dc_.patch
deleted file mode 100644
index ef7a4525..00000000
--- a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4752-drm-amd-display-replace-clocks_value-struct-with-dc_.patch
+++ /dev/null
@@ -1,378 +0,0 @@
-From 2debb6972a470ed43081814f6f9161dd32ce7916 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Wed, 23 May 2018 13:16:50 -0400
-Subject: [PATCH 4752/5725] drm/amd/display: replace clocks_value struct with
- dc_clocks
-
-This will avoid structs with duplicate information. Also
-removes pixel clock voltage request. This has no effect since
-pixel clock does not affect dcn voltage and this function only
-matters for dcn.
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 34 ++++++++--------
- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 ++--
- drivers/gpu/drm/amd/display/dc/dc.h | 5 +++
- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 46 ++++++++--------------
- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 18 +--------
- drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 2 +-
- .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 22 ++---------
- 7 files changed, 49 insertions(+), 86 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
-index 49a4ea4..d8a3165 100644
---- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
-+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
-@@ -1145,10 +1145,10 @@ static unsigned int dcn_find_normalized_clock_vdd_Level(
-
- switch (clocks_type) {
- case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
-- if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
-+ /*if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
- vdd_level = dcn_bw_v_max0p91;
-- BREAK_TO_DEBUGGER();
-- } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
-+ //BREAK_TO_DEBUGGER();
-+ } else*/ if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
- vdd_level = dcn_bw_v_max0p9;
- } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {
- vdd_level = dcn_bw_v_nom0p8;
-@@ -1158,10 +1158,10 @@ static unsigned int dcn_find_normalized_clock_vdd_Level(
- vdd_level = dcn_bw_v_min0p65;
- break;
- case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
-- if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
-+ /*if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
- vdd_level = dcn_bw_v_max0p91;
- BREAK_TO_DEBUGGER();
-- } else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
-+ } else*/ if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
- vdd_level = dcn_bw_v_max0p9;
- } else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {
- vdd_level = dcn_bw_v_nom0p8;
-@@ -1172,10 +1172,10 @@ static unsigned int dcn_find_normalized_clock_vdd_Level(
- break;
-
- case DM_PP_CLOCK_TYPE_DPPCLK:
-- if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {
-+ /*if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {
- vdd_level = dcn_bw_v_max0p91;
- BREAK_TO_DEBUGGER();
-- } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {
-+ } else*/ if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {
- vdd_level = dcn_bw_v_max0p9;
- } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {
- vdd_level = dcn_bw_v_nom0p8;
-@@ -1189,10 +1189,10 @@ static unsigned int dcn_find_normalized_clock_vdd_Level(
- {
- unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
-
-- if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
-+ /*if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
- vdd_level = dcn_bw_v_max0p91;
- BREAK_TO_DEBUGGER();
-- } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
-+ } else */if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
- vdd_level = dcn_bw_v_max0p9;
- } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
- vdd_level = dcn_bw_v_nom0p8;
-@@ -1204,10 +1204,10 @@ static unsigned int dcn_find_normalized_clock_vdd_Level(
- break;
-
- case DM_PP_CLOCK_TYPE_DCFCLK:
-- if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {
-+ /*if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {
- vdd_level = dcn_bw_v_max0p91;
- BREAK_TO_DEBUGGER();
-- } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {
-+ } else */if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {
- vdd_level = dcn_bw_v_max0p9;
- } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {
- vdd_level = dcn_bw_v_nom0p8;
-@@ -1225,27 +1225,27 @@ static unsigned int dcn_find_normalized_clock_vdd_Level(
-
- unsigned int dcn_find_dcfclk_suits_all(
- const struct dc *dc,
-- struct clocks_value *clocks)
-+ struct dc_clocks *clocks)
- {
- unsigned vdd_level, vdd_level_temp;
- unsigned dcf_clk;
-
- /*find a common supported voltage level*/
- vdd_level = dcn_find_normalized_clock_vdd_Level(
-- dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_in_khz);
-+ dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz);
- vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
-- dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_in_khz);
-+ dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);
-
- vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
- vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
-- dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_in_khz);
-+ dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
- vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
-
- vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
-- dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->dcfclock_in_khz);
-+ dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz);
- vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
- vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
-- dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclock_in_khz);
-+ dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz);
-
- /*find that level conresponding dcfclk*/
- vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
-diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
-index 53f9db9..af9e0db 100644
---- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
-@@ -1290,15 +1290,13 @@ static enum dc_status enable_link_dp(
- state->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL);
- } else {
- uint32_t dp_phyclk_in_khz;
-- const struct clocks_value clocks_value =
-- state->dis_clk->cur_clocks_value;
-+ const struct dc_clocks clocks_value =
-+ state->dis_clk->clks;
-
- /* 27mhz = 27000000hz= 27000khz */
- dp_phyclk_in_khz = link_settings.link_rate * 27000;
-
-- if (((clocks_value.max_non_dp_phyclk_in_khz != 0) &&
-- (dp_phyclk_in_khz > clocks_value.max_non_dp_phyclk_in_khz)) ||
-- (dp_phyclk_in_khz > clocks_value.max_dp_phyclk_in_khz)) {
-+ if (dp_phyclk_in_khz > clocks_value.phyclk_khz) {
- state->dis_clk->funcs->apply_clock_voltage_request(
- state->dis_clk,
- DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
-diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
-index 56c1e2b..3471485 100644
---- a/drivers/gpu/drm/amd/display/dc/dc.h
-+++ b/drivers/gpu/drm/amd/display/dc/dc.h
-@@ -187,6 +187,10 @@ enum wm_report_mode {
- WM_REPORT_OVERRIDE = 1,
- };
-
-+/*
-+ * For any clocks that may differ per pipe
-+ * only the max is stored in this structure
-+ */
- struct dc_clocks {
- int dispclk_khz;
- int max_supported_dppclk_khz;
-@@ -195,6 +199,7 @@ struct dc_clocks {
- int socclk_khz;
- int dcfclk_deep_sleep_khz;
- int fclk_khz;
-+ int phyclk_khz;
- };
-
- struct dc_debug {
-diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
-index 8a581c6..b749a20 100644
---- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
-+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
-@@ -560,11 +560,9 @@ static bool dce_apply_clock_voltage_request(
-
- switch (clocks_type) {
- case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
-- case DM_PP_CLOCK_TYPE_PIXELCLK:
- case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
- break;
- default:
-- BREAK_TO_DEBUGGER();
- return false;
- }
-
-@@ -575,31 +573,22 @@ static bool dce_apply_clock_voltage_request(
- if (pre_mode_set) {
- switch (clocks_type) {
- case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
-- if (clocks_in_khz > clk->cur_clocks_value.dispclk_in_khz) {
-- clk->cur_clocks_value.dispclk_notify_pplib_done = true;
-+ if (clocks_in_khz > clk->clks.dispclk_khz) {
-+ clk->dispclk_notify_pplib_done = true;
- send_request = true;
- } else
-- clk->cur_clocks_value.dispclk_notify_pplib_done = false;
-+ clk->dispclk_notify_pplib_done = false;
- /* no matter incrase or decrase clock, update current clock value */
-- clk->cur_clocks_value.dispclk_in_khz = clocks_in_khz;
-- break;
-- case DM_PP_CLOCK_TYPE_PIXELCLK:
-- if (clocks_in_khz > clk->cur_clocks_value.max_pixelclk_in_khz) {
-- clk->cur_clocks_value.pixelclk_notify_pplib_done = true;
-- send_request = true;
-- } else
-- clk->cur_clocks_value.pixelclk_notify_pplib_done = false;
-- /* no matter incrase or decrase clock, update current clock value */
-- clk->cur_clocks_value.max_pixelclk_in_khz = clocks_in_khz;
-+ clk->clks.dispclk_khz = clocks_in_khz;
- break;
- case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
-- if (clocks_in_khz > clk->cur_clocks_value.max_non_dp_phyclk_in_khz) {
-- clk->cur_clocks_value.phyclk_notigy_pplib_done = true;
-+ if (clocks_in_khz > clk->clks.phyclk_khz) {
-+ clk->phyclk_notify_pplib_done = true;
- send_request = true;
- } else
-- clk->cur_clocks_value.phyclk_notigy_pplib_done = false;
-+ clk->phyclk_notify_pplib_done = false;
- /* no matter incrase or decrase clock, update current clock value */
-- clk->cur_clocks_value.max_non_dp_phyclk_in_khz = clocks_in_khz;
-+ clk->clks.phyclk_khz = clocks_in_khz;
- break;
- default:
- ASSERT(0);
-@@ -609,16 +598,14 @@ static bool dce_apply_clock_voltage_request(
- } else {
- switch (clocks_type) {
- case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
-- if (!clk->cur_clocks_value.dispclk_notify_pplib_done)
-- send_request = true;
-- break;
-- case DM_PP_CLOCK_TYPE_PIXELCLK:
-- if (!clk->cur_clocks_value.pixelclk_notify_pplib_done)
-+ if (!clk->dispclk_notify_pplib_done)
- send_request = true;
-+ clk->dispclk_notify_pplib_done = true;
- break;
- case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
-- if (!clk->cur_clocks_value.phyclk_notigy_pplib_done)
-+ if (!clk->phyclk_notify_pplib_done)
- send_request = true;
-+ clk->phyclk_notify_pplib_done = true;
- break;
- default:
- ASSERT(0);
-@@ -627,20 +614,21 @@ static bool dce_apply_clock_voltage_request(
- }
- if (send_request) {
- #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-- if (clk->ctx->dce_version >= DCN_VERSION_1_0) {
-+ if (clk->ctx->dce_version >= DCN_VERSION_1_0
-+ ) {
- struct dc *core_dc = clk->ctx->dc;
- /*use dcfclk request voltage*/
- clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
- clock_voltage_req.clocks_in_khz =
-- dcn_find_dcfclk_suits_all(core_dc, &clk->cur_clocks_value);
-+ dcn_find_dcfclk_suits_all(core_dc, &clk->clks);
- }
- #endif
- dm_pp_apply_clock_for_voltage_request(
- clk->ctx, &clock_voltage_req);
- }
- if (update_dp_phyclk && (clocks_in_khz >
-- clk->cur_clocks_value.max_dp_phyclk_in_khz))
-- clk->cur_clocks_value.max_dp_phyclk_in_khz = clocks_in_khz;
-+ clk->clks.phyclk_khz))
-+ clk->clks.phyclk_khz = clocks_in_khz;
-
- return true;
- }
-diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
-index 57d8113..e540172 100644
---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
-@@ -1800,21 +1800,14 @@ static void apply_min_clocks(
- context->dis_clk->funcs->apply_clock_voltage_request(
- context->dis_clk,
- DM_PP_CLOCK_TYPE_DISPLAY_CLK,
-- context->dis_clk->cur_clocks_value.dispclk_in_khz,
-- pre_mode_set,
-- false);
--
-- context->dis_clk->funcs->apply_clock_voltage_request(
-- context->dis_clk,
-- DM_PP_CLOCK_TYPE_PIXELCLK,
-- context->dis_clk->cur_clocks_value.max_pixelclk_in_khz,
-+ context->dis_clk->clks.dispclk_khz,
- pre_mode_set,
- false);
-
- context->dis_clk->funcs->apply_clock_voltage_request(
- context->dis_clk,
- DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
-- context->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz,
-+ context->dis_clk->clks.phyclk_khz,
- pre_mode_set,
- false);
- return;
-@@ -1843,13 +1836,6 @@ static void apply_min_clocks(
-
- context->dis_clk->funcs->apply_clock_voltage_request(
- context->dis_clk,
-- DM_PP_CLOCK_TYPE_PIXELCLK,
-- req_clocks.pixel_clk_khz,
-- pre_mode_set,
-- false);
--
-- context->dis_clk->funcs->apply_clock_voltage_request(
-- context->dis_clk,
- DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
- req_clocks.pixel_clk_khz,
- pre_mode_set,
-diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
-index 132d18d..ddbb673 100644
---- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
-+++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
-@@ -625,7 +625,7 @@ bool dcn_validate_bandwidth(
-
- unsigned int dcn_find_dcfclk_suits_all(
- const struct dc *dc,
-- struct clocks_value *clocks);
-+ struct dc_clocks *clocks);
-
- void dcn_bw_update_from_pplib(struct dc *dc);
- void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc);
-diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h
-index f5f69cd..6b9ca55 100644
---- a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h
-+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h
-@@ -27,23 +27,7 @@
- #define __DISPLAY_CLOCK_H__
-
- #include "dm_services_types.h"
--
--
--struct clocks_value {
-- int dispclk_in_khz;
-- int max_pixelclk_in_khz;
-- int max_non_dp_phyclk_in_khz;
-- int max_dp_phyclk_in_khz;
-- bool dispclk_notify_pplib_done;
-- bool pixelclk_notify_pplib_done;
-- bool phyclk_notigy_pplib_done;
-- int dcfclock_in_khz;
-- int dppclk_in_khz;
-- int mclk_in_khz;
-- int phyclk_in_khz;
-- int common_vdd_level;
--};
--
-+#include "dc.h"
-
- /* Structure containing all state-dependent clocks
- * (dependent on "enum clocks_state") */
-@@ -56,9 +40,11 @@ struct display_clock {
- struct dc_context *ctx;
- const struct display_clock_funcs *funcs;
-
-+ bool dispclk_notify_pplib_done;
-+ bool phyclk_notify_pplib_done;
- enum dm_pp_clocks_state max_clks_state;
- enum dm_pp_clocks_state cur_min_clks_state;
-- struct clocks_value cur_clocks_value;
-+ struct dc_clocks clks;
- };
-
- struct display_clock_funcs {
---
-2.7.4
-
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-06-01 12:23:12 +0000