diff options
Diffstat (limited to 'meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4708-drm-amd-powerplay-correct-vega12-bootup-values-setti.patch')
| -rw-r--r-- | meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4708-drm-amd-powerplay-correct-vega12-bootup-values-setti.patch | 183 |
1 files changed, 0 insertions, 183 deletions
diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4708-drm-amd-powerplay-correct-vega12-bootup-values-setti.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4708-drm-amd-powerplay-correct-vega12-bootup-values-setti.patch deleted file mode 100644 index 28c69fb2..00000000 --- a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4708-drm-amd-powerplay-correct-vega12-bootup-values-setti.patch +++ /dev/null @@ -1,183 +0,0 @@ -From 56c86885423448422d8491e631b8cd80c29a7b0d Mon Sep 17 00:00:00 2001 -From: Evan Quan <evan.quan@amd.com> -Date: Mon, 28 May 2018 08:59:16 +0800 -Subject: [PATCH 4708/5725] drm/amd/powerplay: correct vega12 bootup values - settings - -The vbios firmware structure changed between v3_1 and v3_2. So, -the code to setup bootup values needs different paths based -on header version. - -Signed-off-by: Evan Quan <evan.quan@amd.com> -Acked-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 94 +++++++++++++++++++--- - drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 3 + - drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 3 + - drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h | 3 + - 4 files changed, 91 insertions(+), 12 deletions(-) - -diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c -index 5325661..aa2faff 100644 ---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c -+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c -@@ -512,14 +512,82 @@ int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLKI - return 0; - } - -+static void pp_atomfwctrl_copy_vbios_bootup_values_3_2(struct pp_hwmgr *hwmgr, -+ struct pp_atomfwctrl_bios_boot_up_values *boot_values, -+ struct atom_firmware_info_v3_2 *fw_info) -+{ -+ uint32_t frequency = 0; -+ -+ boot_values->ulRevision = fw_info->firmware_revision; -+ boot_values->ulGfxClk = fw_info->bootup_sclk_in10khz; -+ boot_values->ulUClk = fw_info->bootup_mclk_in10khz; -+ boot_values->usVddc = fw_info->bootup_vddc_mv; -+ boot_values->usVddci = fw_info->bootup_vddci_mv; -+ boot_values->usMvddc = fw_info->bootup_mvddc_mv; -+ boot_values->usVddGfx = fw_info->bootup_vddgfx_mv; -+ boot_values->ucCoolingID = fw_info->coolingsolution_id; -+ boot_values->ulSocClk = 0; -+ boot_values->ulDCEFClk = 0; -+ -+ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_SOCCLK_ID, &frequency)) -+ boot_values->ulSocClk = frequency; -+ -+ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_DCEFCLK_ID, &frequency)) -+ boot_values->ulDCEFClk = frequency; -+ -+ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_ECLK_ID, &frequency)) -+ boot_values->ulEClk = frequency; -+ -+ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_VCLK_ID, &frequency)) -+ boot_values->ulVClk = frequency; -+ -+ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_DCLK_ID, &frequency)) -+ boot_values->ulDClk = frequency; -+} -+ -+static void pp_atomfwctrl_copy_vbios_bootup_values_3_1(struct pp_hwmgr *hwmgr, -+ struct pp_atomfwctrl_bios_boot_up_values *boot_values, -+ struct atom_firmware_info_v3_1 *fw_info) -+{ -+ uint32_t frequency = 0; -+ -+ boot_values->ulRevision = fw_info->firmware_revision; -+ boot_values->ulGfxClk = fw_info->bootup_sclk_in10khz; -+ boot_values->ulUClk = fw_info->bootup_mclk_in10khz; -+ boot_values->usVddc = fw_info->bootup_vddc_mv; -+ boot_values->usVddci = fw_info->bootup_vddci_mv; -+ boot_values->usMvddc = fw_info->bootup_mvddc_mv; -+ boot_values->usVddGfx = fw_info->bootup_vddgfx_mv; -+ boot_values->ucCoolingID = fw_info->coolingsolution_id; -+ boot_values->ulSocClk = 0; -+ boot_values->ulDCEFClk = 0; -+ -+ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_SOCCLK_ID, &frequency)) -+ boot_values->ulSocClk = frequency; -+ -+ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCEFCLK_ID, &frequency)) -+ boot_values->ulDCEFClk = frequency; -+ -+ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_ECLK_ID, &frequency)) -+ boot_values->ulEClk = frequency; -+ -+ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_VCLK_ID, &frequency)) -+ boot_values->ulVClk = frequency; -+ -+ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCLK_ID, &frequency)) -+ boot_values->ulDClk = frequency; -+} -+ - int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, - struct pp_atomfwctrl_bios_boot_up_values *boot_values) - { -- struct atom_firmware_info_v3_1 *info = NULL; -+ struct atom_firmware_info_v3_2 *fwinfo_3_2; -+ struct atom_firmware_info_v3_1 *fwinfo_3_1; -+ struct atom_common_table_header *info = NULL; - uint16_t ix; - - ix = GetIndexIntoMasterDataTable(firmwareinfo); -- info = (struct atom_firmware_info_v3_1 *) -+ info = (struct atom_common_table_header *) - smu_atom_get_data_table(hwmgr->adev, - ix, NULL, NULL, NULL); - -@@ -528,16 +596,18 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, - return -EINVAL; - } - -- boot_values->ulRevision = info->firmware_revision; -- boot_values->ulGfxClk = info->bootup_sclk_in10khz; -- boot_values->ulUClk = info->bootup_mclk_in10khz; -- boot_values->usVddc = info->bootup_vddc_mv; -- boot_values->usVddci = info->bootup_vddci_mv; -- boot_values->usMvddc = info->bootup_mvddc_mv; -- boot_values->usVddGfx = info->bootup_vddgfx_mv; -- boot_values->ucCoolingID = info->coolingsolution_id; -- boot_values->ulSocClk = 0; -- boot_values->ulDCEFClk = 0; -+ if ((info->format_revision == 3) && (info->content_revision == 2)) { -+ fwinfo_3_2 = (struct atom_firmware_info_v3_2 *)info; -+ pp_atomfwctrl_copy_vbios_bootup_values_3_2(hwmgr, -+ boot_values, fwinfo_3_2); -+ } else if ((info->format_revision == 3) && (info->content_revision == 1)) { -+ fwinfo_3_1 = (struct atom_firmware_info_v3_1 *)info; -+ pp_atomfwctrl_copy_vbios_bootup_values_3_1(hwmgr, -+ boot_values, fwinfo_3_1); -+ } else { -+ pr_info("Fw info table revision does not match!"); -+ return -EINVAL; -+ } - - return 0; - } -diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h -index fe10aa4..745bd38 100644 ---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h -+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h -@@ -136,6 +136,9 @@ struct pp_atomfwctrl_bios_boot_up_values { - uint32_t ulUClk; - uint32_t ulSocClk; - uint32_t ulDCEFClk; -+ uint32_t ulEClk; -+ uint32_t ulVClk; -+ uint32_t ulDClk; - uint16_t usVddc; - uint16_t usVddci; - uint16_t usMvddc; -diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c -index b38b1d9..6e22cb3 100644 ---- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c -+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c -@@ -804,6 +804,9 @@ static int vega12_init_smc_table(struct pp_hwmgr *hwmgr) - data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; - data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; - data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID; -+ data->vbios_boot_state.eclock = boot_up_values.ulEClk; -+ data->vbios_boot_state.dclock = boot_up_values.ulDClk; -+ data->vbios_boot_state.vclock = boot_up_values.ulVClk; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetMinDeepSleepDcefclk, - (uint32_t)(data->vbios_boot_state.dcef_clock / 100)); -diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h -index e81ded1..49b38df 100644 ---- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h -+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h -@@ -167,6 +167,9 @@ struct vega12_vbios_boot_state { - uint32_t mem_clock; - uint32_t soc_clock; - uint32_t dcef_clock; -+ uint32_t eclock; -+ uint32_t dclock; -+ uint32_t vclock; - }; - - #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 --- -2.7.4 - |