diff options
Diffstat (limited to 'meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4400-drm-amdgpu-sdma4-Add-vega20-golden-settings-v3.patch')
| -rw-r--r-- | meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4400-drm-amdgpu-sdma4-Add-vega20-golden-settings-v3.patch | 64 |
1 files changed, 0 insertions, 64 deletions
diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4400-drm-amdgpu-sdma4-Add-vega20-golden-settings-v3.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4400-drm-amdgpu-sdma4-Add-vega20-golden-settings-v3.patch deleted file mode 100644 index 0a449d4d..00000000 --- a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/4400-drm-amdgpu-sdma4-Add-vega20-golden-settings-v3.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 472dd302f317f8ebd000451d3c068a919ad5c4d2 Mon Sep 17 00:00:00 2001 -From: Feifei Xu <Feifei.Xu@amd.com> -Date: Tue, 23 Jan 2018 11:13:02 +0800 -Subject: [PATCH 4400/5725] drm/amdgpu/sdma4: Add vega20 golden settings (v3) - -v2: squash in updates (Alex) -v3: squash in more updates (Alex) - -Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c -index 3c10f54..b1114e5 100644 ---- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c -@@ -109,6 +109,28 @@ static const struct soc15_reg_golden golden_settings_sdma_4_1[] = - SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0) - }; - -+static const struct soc15_reg_golden golden_settings_sdma_4_2[] = -+{ -+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), -+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), -+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), -+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), -+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), -+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), -+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), -+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), -+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), -+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), -+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), -+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), -+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), -+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), -+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), -+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), -+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), -+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0) -+}; -+ - static const struct soc15_reg_golden golden_settings_sdma_rv1[] = - { - SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), -@@ -141,6 +163,11 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) - golden_settings_sdma_vg12, - ARRAY_SIZE(golden_settings_sdma_vg12)); - break; -+ case CHIP_VEGA20: -+ soc15_program_register_sequence(adev, -+ golden_settings_sdma_4_2, -+ ARRAY_SIZE(golden_settings_sdma_4_2)); -+ break; - case CHIP_RAVEN: - soc15_program_register_sequence(adev, - golden_settings_sdma_4_1, --- -2.7.4 - |