diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4689-drm-amd-display-Reset-steer-fifo-before-unblanking-t.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4689-drm-amd-display-Reset-steer-fifo-before-unblanking-t.patch | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4689-drm-amd-display-Reset-steer-fifo-before-unblanking-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4689-drm-amd-display-Reset-steer-fifo-before-unblanking-t.patch new file mode 100644 index 00000000..1d5fcbee --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4689-drm-amd-display-Reset-steer-fifo-before-unblanking-t.patch @@ -0,0 +1,56 @@ +From fc58a25e03e6f56115fda22aab113533d1932c93 Mon Sep 17 00:00:00 2001 +From: Nikola Cornij <nikola.cornij@amd.com> +Date: Mon, 11 Nov 2019 18:03:59 -0500 +Subject: [PATCH 4689/4736] drm/amd/display: Reset steer fifo before unblanking + the stream + +[why] +During mode transition steer fifo could overflow. Quite often it +recovers by itself, but sometimes it doesn't. + +[how] +Add steer fifo reset before unblanking the stream. Also add a short +delay when resetting dig resync fifo to make sure register writes +don't end up back-to-back, in which case the HW might miss the reset +request. + +Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c +index 3549c81b20b7..99f33c7ae528 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c +@@ -486,15 +486,23 @@ void enc2_stream_encoder_dp_unblank( + DP_VID_N_MUL, n_multiply); + } + +- /* set DIG_START to 0x1 to reset FIFO */ ++ /* make sure stream is disabled before resetting steer fifo */ ++ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); ++ REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); + ++ /* set DIG_START to 0x1 to reset FIFO */ + REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); ++ udelay(1); + + /* write 0 to take the FIFO out of reset */ + + REG_UPDATE(DIG_FE_CNTL, DIG_START, 0); + +- /* switch DP encoder to CRTC data */ ++ /* switch DP encoder to CRTC data, but reset it the fifo first. It may happen ++ * that it overflows during mode transition, and sometimes doesn't recover. ++ */ ++ REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1); ++ udelay(10); + + REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); + +-- +2.17.1 + |