diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4681-drm-amd-display-have-two-different-sr-and-pstate-lat.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4681-drm-amd-display-have-two-different-sr-and-pstate-lat.patch | 164 |
1 files changed, 164 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4681-drm-amd-display-have-two-different-sr-and-pstate-lat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4681-drm-amd-display-have-two-different-sr-and-pstate-lat.patch new file mode 100644 index 00000000..f7407cc3 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4681-drm-amd-display-have-two-different-sr-and-pstate-lat.patch @@ -0,0 +1,164 @@ +From 14f863bbcbc727e06ca1257e9802fb6cf74a0b60 Mon Sep 17 00:00:00 2001 +From: Joseph Gravenor <joseph.gravenor@amd.com> +Date: Fri, 8 Nov 2019 14:30:34 -0500 +Subject: [PATCH 4681/4736] drm/amd/display: have two different sr and pstate + latency tables for renoir + +[Why] +new sr and pstate latencies are optimized for the case when we are not +using lpddr4 memory + +[How] +have two different wm tables, one for the lpddr case and one for +non lpddr case + +Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> +Reviewed-by: Eric Yang <eric.yang2@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 114 ++++++++++++------ + 1 file changed, 80 insertions(+), 34 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +index 9f0381c68844..89ed230cdb26 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +@@ -518,44 +518,83 @@ struct clk_bw_params rn_bw_params = { + .num_entries = 4, + }, + +- .wm_table = { +- .entries = { +- { +- .wm_inst = WM_A, +- .wm_type = WM_TYPE_PSTATE_CHG, +- .pstate_latency_us = 11.72, +- .sr_exit_time_us = 6.09, +- .sr_enter_plus_exit_time_us = 7.14, +- .valid = true, +- }, +- { +- .wm_inst = WM_B, +- .wm_type = WM_TYPE_PSTATE_CHG, +- .pstate_latency_us = 11.72, +- .sr_exit_time_us = 10.12, +- .sr_enter_plus_exit_time_us = 11.48, +- .valid = true, +- }, +- { +- .wm_inst = WM_C, +- .wm_type = WM_TYPE_PSTATE_CHG, +- .pstate_latency_us = 11.72, +- .sr_exit_time_us = 10.12, +- .sr_enter_plus_exit_time_us = 11.48, +- .valid = true, +- }, +- { +- .wm_inst = WM_D, +- .wm_type = WM_TYPE_PSTATE_CHG, +- .pstate_latency_us = 11.72, +- .sr_exit_time_us = 10.12, +- .sr_enter_plus_exit_time_us = 11.48, +- .valid = true, +- }, ++}; ++ ++struct wm_table ddr4_wm_table = { ++ .entries = { ++ { ++ .wm_inst = WM_A, ++ .wm_type = WM_TYPE_PSTATE_CHG, ++ .pstate_latency_us = 11.72, ++ .sr_exit_time_us = 6.09, ++ .sr_enter_plus_exit_time_us = 7.14, ++ .valid = true, ++ }, ++ { ++ .wm_inst = WM_B, ++ .wm_type = WM_TYPE_PSTATE_CHG, ++ .pstate_latency_us = 11.72, ++ .sr_exit_time_us = 10.12, ++ .sr_enter_plus_exit_time_us = 11.48, ++ .valid = true, ++ }, ++ { ++ .wm_inst = WM_C, ++ .wm_type = WM_TYPE_PSTATE_CHG, ++ .pstate_latency_us = 11.72, ++ .sr_exit_time_us = 10.12, ++ .sr_enter_plus_exit_time_us = 11.48, ++ .valid = true, ++ }, ++ { ++ .wm_inst = WM_D, ++ .wm_type = WM_TYPE_PSTATE_CHG, ++ .pstate_latency_us = 11.72, ++ .sr_exit_time_us = 10.12, ++ .sr_enter_plus_exit_time_us = 11.48, ++ .valid = true, + }, + } + }; + ++struct wm_table lpddr4_wm_table = { ++ .entries = { ++ { ++ .wm_inst = WM_A, ++ .wm_type = WM_TYPE_PSTATE_CHG, ++ .pstate_latency_us = 23.84, ++ .sr_exit_time_us = 12.5, ++ .sr_enter_plus_exit_time_us = 17.0, ++ .valid = true, ++ }, ++ { ++ .wm_inst = WM_B, ++ .wm_type = WM_TYPE_PSTATE_CHG, ++ .pstate_latency_us = 23.84, ++ .sr_exit_time_us = 12.5, ++ .sr_enter_plus_exit_time_us = 17.0, ++ .valid = true, ++ }, ++ { ++ .wm_inst = WM_C, ++ .wm_type = WM_TYPE_PSTATE_CHG, ++ .pstate_latency_us = 23.84, ++ .sr_exit_time_us = 12.5, ++ .sr_enter_plus_exit_time_us = 17.0, ++ .valid = true, ++ }, ++ { ++ .wm_inst = WM_D, ++ .wm_type = WM_TYPE_PSTATE_CHG, ++ .pstate_latency_us = 23.84, ++ .sr_exit_time_us = 12.5, ++ .sr_enter_plus_exit_time_us = 17.0, ++ .valid = true, ++ }, ++ } ++}; ++ ++ + static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage) + { + int i; +@@ -677,10 +716,17 @@ void rn_clk_mgr_construct( + ASSERT(clk_mgr->base.dprefclk_khz == 600000); + clk_mgr->base.dprefclk_khz = 600000; + } ++ ++ if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) { ++ rn_bw_params.wm_table = lpddr4_wm_table; ++ } else { ++ rn_bw_params.wm_table = ddr4_wm_table; ++ } + } + + dce_clock_read_ss_info(clk_mgr); + ++ + clk_mgr->base.bw_params = &rn_bw_params; + + if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) { +-- +2.17.1 + |