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-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4670-drm-amd-display-Map-DSC-resources-1-to-1-if-numbers-.patch72
1 files changed, 72 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4670-drm-amd-display-Map-DSC-resources-1-to-1-if-numbers-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4670-drm-amd-display-Map-DSC-resources-1-to-1-if-numbers-.patch
new file mode 100644
index 00000000..3b5227d8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4670-drm-amd-display-Map-DSC-resources-1-to-1-if-numbers-.patch
@@ -0,0 +1,72 @@
+From 9666c46fe746cf775aef8e3a8470ab4e62c15f00 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Thu, 7 Nov 2019 13:06:48 -0500
+Subject: [PATCH 4670/4736] drm/amd/display: Map DSC resources 1-to-1 if
+ numbers of OPPs and DSCs are equal
+
+[why]
+On ASICs where number of DSCs is the same as OPPs there's no need
+for DSC resource management. Mappping 1-to-1 fixes mode-set- or S3-
+-related issues for such platforms.
+
+[how]
+Map DSC resources 1-to-1 to pipes only if number of OPPs is the same
+as number of DSCs. This will still keep other ASICs working.
+A follow-up patch to fix mode-set issues on those ASICs will be
+required if testing shows issues with mode set.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index b000d5289684..2e03ff357746 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1524,13 +1524,20 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state
+
+ static void acquire_dsc(struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+- struct display_stream_compressor **dsc)
++ struct display_stream_compressor **dsc,
++ int pipe_idx)
+ {
+ int i;
+
+ ASSERT(*dsc == NULL);
+ *dsc = NULL;
+
++ if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
++ *dsc = pool->dscs[pipe_idx];
++ res_ctx->is_dsc_acquired[pipe_idx] = true;
++ return;
++ }
++
+ /* Find first free DSC */
+ for (i = 0; i < pool->res_cap->num_dsc; i++)
+ if (!res_ctx->is_dsc_acquired[i]) {
+@@ -1571,7 +1578,7 @@ static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
+ if (pipe_ctx->stream != dc_stream)
+ continue;
+
+- acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);
++ acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i);
+
+ /* The number of DSCs can be less than the number of pipes */
+ if (!pipe_ctx->stream_res.dsc) {
+@@ -1763,7 +1770,7 @@ bool dcn20_split_stream_for_odm(
+ }
+ next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
+ if (next_odm_pipe->stream->timing.flags.DSC == 1) {
+- acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc);
++ acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
+ ASSERT(next_odm_pipe->stream_res.dsc);
+ if (next_odm_pipe->stream_res.dsc == NULL)
+ return false;
+--
+2.17.1
+