1 files changed, 780 insertions, 0 deletions

diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4667-drm-amd-display-rename-core_dc-to-dc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4667-drm-amd-display-rename-core_dc-to-dc.patch
new file mode 100644
index 00000000..8a62c75b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4667-drm-amd-display-rename-core_dc-to-dc.patch
@@ -0,0 +1,780 @@
+From 34231c7e48957fe66cb6f6469c55a2f267fda105 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Tue, 5 Nov 2019 13:04:34 -0500
+Subject: [PATCH 4667/4736] drm/amd/display: rename core_dc to dc
+
+[Why]
+First, to make code more consistent
+Second, to get rid of those scenario where we create a second
+local pointer to dc when it's already passed in.
+
+[How]
+Rename core_dc to dc
+Remove duplicate local pointers to dc
+
+Change-Id: Ibace3c21e3722d874f36567a2e240e2112ba2b17
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../dc/clk_mgr/dce112/dce112_clk_mgr.c        | 12 ++--
+ .../dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c  |  6 +-
+ .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   |  6 +-
+ .../gpu/drm/amd/display/dc/core/dc_debug.c    |  7 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 64 +++++++++----------
+ .../drm/amd/display/dc/core/dc_link_hwss.c    | 26 ++++----
+ .../gpu/drm/amd/display/dc/core/dc_resource.c |  3 +-
+ .../gpu/drm/amd/display/dc/core/dc_stream.c   | 40 ++++++------
+ .../gpu/drm/amd/display/dc/core/dc_surface.c  | 22 +++----
+ .../display/dc/dce110/dce110_hw_sequencer.c   |  8 +--
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +--
+ .../dc/irq/dce110/irq_service_dce110.c        |  4 +-
+ 12 files changed, 102 insertions(+), 106 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+index a6c46e903ff9..d031bd3d3072 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+@@ -72,8 +72,8 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
+ 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+ 	struct bp_set_dce_clock_parameters dce_clk_params;
+ 	struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
+-	struct dc *core_dc = clk_mgr_base->ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc *dc = clk_mgr_base->ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 	int actual_clock = requested_clk_khz;
+ 	/* Prepare to program display clock*/
+ 	memset(&dce_clk_params, 0, sizeof(dce_clk_params));
+@@ -110,7 +110,7 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
+ 
+ 	bp->funcs->set_dce_clock(bp, &dce_clk_params);
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ 			if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
+ 				dmcu->funcs->set_psr_wait_loop(dmcu,
+@@ -126,8 +126,8 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
+ {
+ 	struct bp_set_dce_clock_parameters dce_clk_params;
+ 	struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
+-	struct dc *core_dc = clk_mgr->base.ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc *dc = clk_mgr->base.ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 	int actual_clock = requested_clk_khz;
+ 	/* Prepare to program display clock*/
+ 	memset(&dce_clk_params, 0, sizeof(dce_clk_params));
+@@ -152,7 +152,7 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
+ 		clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
+ 
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ 			if (clk_mgr->dfs_bypass_disp_clk != actual_clock)
+ 				dmcu->funcs->set_psr_wait_loop(dmcu,
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+index 1897e91c8ccb..97b7f32294fd 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+@@ -88,8 +88,8 @@ int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned
+ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
+ {
+ 	int actual_dispclk_set_mhz = -1;
+-	struct dc *core_dc = clk_mgr->base.ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc *dc = clk_mgr->base.ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 
+ 	/*  Unit of SMU msg parameter is Mhz */
+ 	actual_dispclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
+@@ -100,7 +100,7 @@ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_di
+ 	/* Actual dispclk set is returned in the parameter register */
+ 	actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ 			if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
+ 				dmcu->funcs->set_psr_wait_loop(dmcu,
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+index cb7c0e8b7e1b..6878aedf1d3e 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -82,8 +82,8 @@ int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
+ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
+ {
+ 	int actual_dispclk_set_mhz = -1;
+-	struct dc *core_dc = clk_mgr->base.ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc *dc = clk_mgr->base.ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 
+ 	/*  Unit of SMU msg parameter is Mhz */
+ 	actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param(
+@@ -91,7 +91,7 @@ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dis
+ 			VBIOSSMC_MSG_SetDispclkFreq,
+ 			requested_dispclk_khz / 1000);
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ 			if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
+ 				dmcu->funcs->set_psr_wait_loop(dmcu,
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+index b9227d5de3a3..5203159ad519 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+@@ -310,14 +310,13 @@ void context_timing_trace(
+ 		struct resource_context *res_ctx)
+ {
+ 	int i;
+-	struct dc  *core_dc = dc;
+ 	int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0};
+ 	struct crtc_position position;
+-	unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
++	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
+ 	DC_LOGGER_INIT(dc->ctx->logger);
+ 
+ 
+-	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
+ 		/* get_position() returns CRTC vertical/horizontal counter
+ 		 * hence not applicable for underlay pipe
+@@ -329,7 +328,7 @@ void context_timing_trace(
+ 		h_pos[i] = position.horizontal_count;
+ 		v_pos[i] = position.vertical_count;
+ 	}
+-	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
+ 
+ 		if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index f27921e46937..9f53cbcc7152 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2353,9 +2353,9 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
+ 		uint32_t backlight_pwm_u16_16,
+ 		uint32_t frame_ramp)
+ {
+-	struct dc  *core_dc = link->ctx->dc;
+-	struct abm *abm = core_dc->res_pool->abm;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc  *dc = link->ctx->dc;
++	struct abm *abm = dc->res_pool->abm;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 	unsigned int controller_id = 0;
+ 	bool use_smooth_brightness = true;
+ 	int i;
+@@ -2373,22 +2373,22 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
+ 
+ 	if (dc_is_embedded_signal(link->connector_signal)) {
+ 		for (i = 0; i < MAX_PIPES; i++) {
+-			if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
+-				if (core_dc->current_state->res_ctx.
++			if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
++				if (dc->current_state->res_ctx.
+ 						pipe_ctx[i].stream->link
+ 						== link) {
+ 					/* DMCU -1 for all controller id values,
+ 					 * therefore +1 here
+ 					 */
+ 					controller_id =
+-						core_dc->current_state->
++						dc->current_state->
+ 						res_ctx.pipe_ctx[i].stream_res.tg->inst +
+ 						1;
+ 
+ 					/* Disable brightness ramping when the display is blanked
+ 					 * as it can hang the DMCU
+ 					 */
+-					if (core_dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
++					if (dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
+ 						frame_ramp = 0;
+ 				}
+ 			}
+@@ -2406,8 +2406,8 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
+ 
+ bool dc_link_set_abm_disable(const struct dc_link *link)
+ {
+-	struct dc  *core_dc = link->ctx->dc;
+-	struct abm *abm = core_dc->res_pool->abm;
++	struct dc  *dc = link->ctx->dc;
++	struct abm *abm = dc->res_pool->abm;
+ 
+ 	if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
+ 		return false;
+@@ -2419,8 +2419,8 @@ bool dc_link_set_abm_disable(const struct dc_link *link)
+ 
+ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool wait)
+ {
+-	struct dc  *core_dc = link->ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc  *dc = link->ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 
+ 
+ 
+@@ -2434,8 +2434,8 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool
+ 
+ bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
+ {
+-	struct dc  *core_dc = link->ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc  *dc = link->ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 
+ 	if (dmcu != NULL && link->psr_feature_enabled)
+ 		dmcu->funcs->get_psr_state(dmcu, psr_state);
+@@ -2482,7 +2482,7 @@ bool dc_link_setup_psr(struct dc_link *link,
+ 		const struct dc_stream_state *stream, struct psr_config *psr_config,
+ 		struct psr_context *psr_context)
+ {
+-	struct dc *core_dc;
++	struct dc *dc;
+ 	struct dmcu *dmcu;
+ 	int i;
+ 	/* updateSinkPsrDpcdConfig*/
+@@ -2493,8 +2493,8 @@ bool dc_link_setup_psr(struct dc_link *link,
+ 	if (!link)
+ 		return false;
+ 
+-	core_dc = link->ctx->dc;
+-	dmcu = core_dc->res_pool->dmcu;
++	dc = link->ctx->dc;
++	dmcu = dc->res_pool->dmcu;
+ 
+ 	if (!dmcu)
+ 		return false;
+@@ -2533,13 +2533,13 @@ bool dc_link_setup_psr(struct dc_link *link,
+ 	psr_context->engineId = link->link_enc->preferred_engine;
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+-		if (core_dc->current_state->res_ctx.pipe_ctx[i].stream
++		if (dc->current_state->res_ctx.pipe_ctx[i].stream
+ 				== stream) {
+ 			/* dmcu -1 for all controller id values,
+ 			 * therefore +1 here
+ 			 */
+ 			psr_context->controllerId =
+-				core_dc->current_state->res_ctx.
++				dc->current_state->res_ctx.
+ 				pipe_ctx[i].stream_res.tg->inst + 1;
+ 			break;
+ 		}
+@@ -2903,12 +2903,12 @@ void core_link_enable_stream(
+ 		struct dc_state *state,
+ 		struct pipe_ctx *pipe_ctx)
+ {
+-	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc *dc = pipe_ctx->stream->ctx->dc;
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	enum dc_status status;
+ 	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) &&
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
+ 			dc_is_virtual_signal(pipe_ctx->stream->signal))
+ 		return;
+ 
+@@ -2951,14 +2951,14 @@ void core_link_enable_stream(
+ 			pipe_ctx->stream_res.stream_enc,
+ 			&stream->timing);
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		bool apply_edp_fast_boot_optimization =
+ 			pipe_ctx->stream->apply_edp_fast_boot_optimization;
+ 
+ 		pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
+ 
+ 		resource_build_info_frame(pipe_ctx);
+-		core_dc->hwss.update_info_frame(pipe_ctx);
++		dc->hwss.update_info_frame(pipe_ctx);
+ 
+ 		/* Do not touch link on seamless boot optimization. */
+ 		if (pipe_ctx->stream->apply_seamless_boot_optimization) {
+@@ -3001,7 +3001,7 @@ void core_link_enable_stream(
+ 			}
+ 		}
+ 
+-		core_dc->hwss.enable_audio_stream(pipe_ctx);
++		dc->hwss.enable_audio_stream(pipe_ctx);
+ 
+ 		/* turn off otg test pattern if enable */
+ 		if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
+@@ -3014,7 +3014,7 @@ void core_link_enable_stream(
+ 					dc_is_virtual_signal(pipe_ctx->stream->signal))
+ 				dp_set_dsc_enable(pipe_ctx, true);
+ 		}
+-		core_dc->hwss.enable_stream(pipe_ctx);
++		dc->hwss.enable_stream(pipe_ctx);
+ 
+ 		/* Set DPS PPS SDP (AKA "info frames") */
+ 		if (pipe_ctx->stream->timing.flags.DSC) {
+@@ -3026,7 +3026,7 @@ void core_link_enable_stream(
+ 		if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+ 			dc_link_allocate_mst_payload(pipe_ctx);
+ 
+-		core_dc->hwss.unblank_stream(pipe_ctx,
++		dc->hwss.unblank_stream(pipe_ctx,
+ 			&pipe_ctx->stream->link->cur_link_settings);
+ 
+ 		if (dc_is_dp_signal(pipe_ctx->stream->signal))
+@@ -3035,7 +3035,7 @@ void core_link_enable_stream(
+ 		update_psp_stream_config(pipe_ctx, false);
+ #endif
+ 	}
+-	else { // if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
++	else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+ 		if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+ 				dc_is_virtual_signal(pipe_ctx->stream->signal))
+ 			dp_set_dsc_enable(pipe_ctx, true);
+@@ -3045,11 +3045,11 @@ void core_link_enable_stream(
+ 
+ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ {
+-	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc  *dc = pipe_ctx->stream->ctx->dc;
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct dc_link *link = stream->sink->link;
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) &&
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
+ 			dc_is_virtual_signal(pipe_ctx->stream->signal))
+ 		return;
+ 
+@@ -3057,7 +3057,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ 	update_psp_stream_config(pipe_ctx, true);
+ #endif
+ 
+-	core_dc->hwss.blank_stream(pipe_ctx);
++	dc->hwss.blank_stream(pipe_ctx);
+ 
+ 	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+ 		deallocate_mst_payload(pipe_ctx);
+@@ -3086,7 +3086,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ 			write_i2c_redriver_setting(pipe_ctx, false);
+ 		}
+ 	}
+-	core_dc->hwss.disable_stream(pipe_ctx);
++	dc->hwss.disable_stream(pipe_ctx);
+ 
+ 	disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
+ 	if (pipe_ctx->stream->timing.flags.DSC) {
+@@ -3097,12 +3097,12 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ 
+ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+-	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc  *dc = pipe_ctx->stream->ctx->dc;
+ 
+ 	if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
+ 		return;
+ 
+-	core_dc->hwss.set_avmute(pipe_ctx, enable);
++	dc->hwss.set_avmute(pipe_ctx, enable);
+ }
+ 
+ /**
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index bb1e8e5b5252..67ce12df23f1 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -95,8 +95,8 @@ void dp_enable_link_phy(
+ 	const struct dc_link_settings *link_settings)
+ {
+ 	struct link_encoder *link_enc = link->link_enc;
+-	struct dc  *core_dc = link->ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc  *dc = link->ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 
+ 	struct pipe_ctx *pipes =
+ 			link->dc->current_state->res_ctx.pipe_ctx;
+@@ -200,8 +200,8 @@ bool edp_receiver_ready_T7(struct dc_link *link)
+ 
+ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
+ {
+-	struct dc  *core_dc = link->ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc  *dc = link->ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 
+ 	if (!link->wa_flags.dp_keep_receiver_powered)
+ 		dp_receiver_power_ctrl(link, false);
+@@ -395,14 +395,14 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc,
+ 
+ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+-	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc *dc = pipe_ctx->stream->ctx->dc;
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	bool result = false;
+ 
+-	if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
++	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+ 		result = true;
+ 	else
+-		result = dm_helpers_dp_write_dsc_enable(core_dc->ctx, stream, enable);
++		result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable);
+ 	return result;
+ }
+ 
+@@ -412,7 +412,7 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
+ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+ 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+-	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc *dc = pipe_ctx->stream->ctx->dc;
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct pipe_ctx *odm_pipe;
+ 	int opp_cnt = 1;
+@@ -448,7 +448,7 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 		optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
+ 
+ 		/* Enable DSC in encoder */
+-		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 			DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
+ 			dsc_optc_config_log(dsc, &dsc_optc_cfg);
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
+@@ -473,7 +473,7 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 				OPTC_DSC_DISABLED, 0, 0);
+ 
+ 		/* disable DSC in stream encoder */
+-		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
+ 					pipe_ctx->stream_res.stream_enc,
+ 					OPTC_DSC_DISABLED, 0, 0);
+@@ -516,7 +516,7 @@ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
+ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+ 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+-	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc *dc = pipe_ctx->stream->ctx->dc;
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 
+ 	if (!pipe_ctx->stream->timing.flags.DSC || !dsc)
+@@ -535,7 +535,7 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
+ 
+ 		DC_LOG_DSC(" ");
+ 		dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
+-		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 			DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
+ 									pipe_ctx->stream_res.stream_enc,
+@@ -544,7 +544,7 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
+ 		}
+ 	} else {
+ 		/* disable DSC PPS in stream encoder */
+-		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
+ 						pipe_ctx->stream_res.stream_enc, false, NULL);
+ 		}
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 081275a430ad..67d1c8cc583b 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -2750,9 +2750,8 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
+ 
+ enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
+ {
+-	struct dc  *core_dc = dc;
+ 	struct dc_link *link = stream->link;
+-	struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
++	struct timing_generator *tg = dc->res_pool->timing_generators[0];
+ 	enum dc_status res = DC_OK;
+ 
+ 	calculate_phy_pix_clks(stream);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index 9029786c7b08..a43b4d7d5a50 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -268,7 +268,7 @@ bool dc_stream_set_cursor_attributes(
+ 	const struct dc_cursor_attributes *attributes)
+ {
+ 	int i;
+-	struct dc  *core_dc;
++	struct dc  *dc;
+ 	struct resource_context *res_ctx;
+ 	struct pipe_ctx *pipe_to_program = NULL;
+ 
+@@ -286,8 +286,8 @@ bool dc_stream_set_cursor_attributes(
+ 		return false;
+ 	}
+ 
+-	core_dc = stream->ctx->dc;
+-	res_ctx = &core_dc->current_state->res_ctx;
++	dc = stream->ctx->dc;
++	res_ctx = &dc->current_state->res_ctx;
+ 	stream->cursor_attributes = *attributes;
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+@@ -299,17 +299,17 @@ bool dc_stream_set_cursor_attributes(
+ 		if (!pipe_to_program) {
+ 			pipe_to_program = pipe_ctx;
+ 
+-			delay_cursor_until_vupdate(pipe_ctx, core_dc);
+-			core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
++			delay_cursor_until_vupdate(pipe_ctx, dc);
++			dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
+ 		}
+ 
+-		core_dc->hwss.set_cursor_attribute(pipe_ctx);
+-		if (core_dc->hwss.set_cursor_sdr_white_level)
+-			core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
++		dc->hwss.set_cursor_attribute(pipe_ctx);
++		if (dc->hwss.set_cursor_sdr_white_level)
++			dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
+ 	}
+ 
+ 	if (pipe_to_program)
+-		core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
++		dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
+ 
+ 	return true;
+ }
+@@ -319,7 +319,7 @@ bool dc_stream_set_cursor_position(
+ 	const struct dc_cursor_position *position)
+ {
+ 	int i;
+-	struct dc  *core_dc;
++	struct dc  *dc;
+ 	struct resource_context *res_ctx;
+ 	struct pipe_ctx *pipe_to_program = NULL;
+ 
+@@ -333,8 +333,8 @@ bool dc_stream_set_cursor_position(
+ 		return false;
+ 	}
+ 
+-	core_dc = stream->ctx->dc;
+-	res_ctx = &core_dc->current_state->res_ctx;
++	dc = stream->ctx->dc;
++	res_ctx = &dc->current_state->res_ctx;
+ 	stream->cursor_position = *position;
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+@@ -350,15 +350,15 @@ bool dc_stream_set_cursor_position(
+ 		if (!pipe_to_program) {
+ 			pipe_to_program = pipe_ctx;
+ 
+-			delay_cursor_until_vupdate(pipe_ctx, core_dc);
+-			core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
++			delay_cursor_until_vupdate(pipe_ctx, dc);
++			dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
+ 		}
+ 
+-		core_dc->hwss.set_cursor_position(pipe_ctx);
++		dc->hwss.set_cursor_position(pipe_ctx);
+ 	}
+ 
+ 	if (pipe_to_program)
+-		core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
++		dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
+ 
+ 	return true;
+ }
+@@ -479,9 +479,9 @@ bool dc_stream_remove_writeback(struct dc *dc,
+ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
+ {
+ 	uint8_t i;
+-	struct dc  *core_dc = stream->ctx->dc;
++	struct dc  *dc = stream->ctx->dc;
+ 	struct resource_context *res_ctx =
+-		&core_dc->current_state->res_ctx;
++		&dc->current_state->res_ctx;
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+ 		struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
+@@ -538,9 +538,9 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
+ {
+ 	uint8_t i;
+ 	bool ret = false;
+-	struct dc  *core_dc = stream->ctx->dc;
++	struct dc  *dc = stream->ctx->dc;
+ 	struct resource_context *res_ctx =
+-		&core_dc->current_state->res_ctx;
++		&dc->current_state->res_ctx;
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+ 		struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+index 5904c459fe8f..834d6145aab4 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+@@ -106,16 +106,14 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
+ 
+ struct dc_plane_state *dc_create_plane_state(struct dc *dc)
+ {
+-	struct dc *core_dc = dc;
+-
+ 	struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),
+-						      GFP_KERNEL);
++							GFP_KERNEL);
+ 
+ 	if (NULL == plane_state)
+ 		return NULL;
+ 
+ 	kref_init(&plane_state->refcount);
+-	dc_plane_construct(core_dc->ctx, plane_state);
++	dc_plane_construct(dc->ctx, plane_state);
+ 
+ 	return plane_state;
+ }
+@@ -135,7 +133,7 @@ const struct dc_plane_status *dc_plane_get_status(
+ 		const struct dc_plane_state *plane_state)
+ {
+ 	const struct dc_plane_status *plane_status;
+-	struct dc  *core_dc;
++	struct dc  *dc;
+ 	int i;
+ 
+ 	if (!plane_state ||
+@@ -146,15 +144,15 @@ const struct dc_plane_status *dc_plane_get_status(
+ 	}
+ 
+ 	plane_status = &plane_state->status;
+-	core_dc = plane_state->ctx->dc;
++	dc = plane_state->ctx->dc;
+ 
+-	if (core_dc->current_state == NULL)
++	if (dc->current_state == NULL)
+ 		return NULL;
+ 
+ 	/* Find the current plane state and set its pending bit to false */
+-	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct pipe_ctx *pipe_ctx =
+-				&core_dc->current_state->res_ctx.pipe_ctx[i];
++				&dc->current_state->res_ctx.pipe_ctx[i];
+ 
+ 		if (pipe_ctx->plane_state != plane_state)
+ 			continue;
+@@ -164,14 +162,14 @@ const struct dc_plane_status *dc_plane_get_status(
+ 		break;
+ 	}
+ 
+-	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct pipe_ctx *pipe_ctx =
+-				&core_dc->current_state->res_ctx.pipe_ctx[i];
++				&dc->current_state->res_ctx.pipe_ctx[i];
+ 
+ 		if (pipe_ctx->plane_state != plane_state)
+ 			continue;
+ 
+-		core_dc->hwss.update_pending_status(pipe_ctx);
++		dc->hwss.update_pending_status(pipe_ctx);
+ 	}
+ 
+ 	return plane_status;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 6291f803cd16..ad53e6727df2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -942,15 +942,15 @@ void dce110_edp_backlight_control(
+ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
+ {
+ 	/* notify audio driver for audio modes of monitor */
+-	struct dc *core_dc;
++	struct dc *dc;
+ 	struct clk_mgr *clk_mgr;
+ 	unsigned int i, num_audio = 1;
+ 
+ 	if (!pipe_ctx->stream)
+ 		return;
+ 
+-	core_dc = pipe_ctx->stream->ctx->dc;
+-	clk_mgr = core_dc->clk_mgr;
++	dc = pipe_ctx->stream->ctx->dc;
++	clk_mgr = dc->clk_mgr;
+ 
+ 	if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
+ 		return;
+@@ -958,7 +958,7 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
+ 	if (pipe_ctx->stream_res.audio) {
+ 		for (i = 0; i < MAX_PIPES; i++) {
+ 			/*current_state not updated yet*/
+-			if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
++			if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
+ 				num_audio++;
+ 		}
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 08d15982f526..1ed26ac33551 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1655,10 +1655,10 @@ void dcn10_enable_per_frame_crtc_position_reset(
+ }
+ 
+ /*static void print_rq_dlg_ttu(
+-		struct dc *core_dc,
++		struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx)
+ {
+-	DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
++	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
+ 			"\n============== DML TTU Output parameters [%d] ==============\n"
+ 			"qos_level_low_wm: %d, \n"
+ 			"qos_level_high_wm: %d, \n"
+@@ -1688,7 +1688,7 @@ void dcn10_enable_per_frame_crtc_position_reset(
+ 			pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
+ 			);
+ 
+-	DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
++	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
+ 			"\n============== DML DLG Output parameters [%d] ==============\n"
+ 			"refcyc_h_blank_end: %d, \n"
+ 			"dlg_vblank_end: %d, \n"
+@@ -1723,7 +1723,7 @@ void dcn10_enable_per_frame_crtc_position_reset(
+ 			pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
+ 			);
+ 
+-	DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
++	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
+ 			"\ndst_y_per_meta_row_nom_l: %d, \n"
+ 			"refcyc_per_meta_chunk_nom_l: %d, \n"
+ 			"refcyc_per_line_delivery_pre_l: %d, \n"
+@@ -1753,7 +1753,7 @@ void dcn10_enable_per_frame_crtc_position_reset(
+ 			pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
+ 			);
+ 
+-	DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
++	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
+ 			"\n============== DML RQ Output parameters [%d] ==============\n"
+ 			"chunk_size: %d \n"
+ 			"min_chunk_size: %d \n"
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+index 80603e18ecd6..662266fc3edf 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+@@ -202,7 +202,7 @@ bool dce110_vblank_set(struct irq_service *irq_service,
+ 		       bool enable)
+ {
+ 	struct dc_context *dc_ctx = irq_service->ctx;
+-	struct dc *core_dc = irq_service->ctx->dc;
++	struct dc *dc = irq_service->ctx->dc;
+ 	enum dc_irq_source dal_irq_src =
+ 			dc_interrupt_to_irq_source(irq_service->ctx->dc,
+ 						   info->src_id,
+@@ -210,7 +210,7 @@ bool dce110_vblank_set(struct irq_service *irq_service,
+ 	uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
+ 
+ 	struct timing_generator *tg =
+-			core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
++			dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
+ 
+ 	if (enable) {
+ 		if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {
+-- 
+2.17.1
+