diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4666-drm-amd-display-update-sr-and-pstate-latencies-for-R.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4666-drm-amd-display-update-sr-and-pstate-latencies-for-R.patch | 119 |
1 files changed, 119 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4666-drm-amd-display-update-sr-and-pstate-latencies-for-R.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4666-drm-amd-display-update-sr-and-pstate-latencies-for-R.patch new file mode 100644 index 00000000..8517952d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4666-drm-amd-display-update-sr-and-pstate-latencies-for-R.patch @@ -0,0 +1,119 @@ +From d8de6521c6f1863d6c364855496b14593e66cda4 Mon Sep 17 00:00:00 2001 +From: Eric Yang <Eric.Yang2@amd.com> +Date: Tue, 5 Nov 2019 11:59:38 -0500 +Subject: [PATCH 4666/4736] drm/amd/display: update sr and pstate latencies for + Renoir + +[Why] +DF team has produced more optimized latency numbers. + +[How] +Add sr latencies to the wm table, use different latencies +for different wm sets. +Also fix bb override from registery key for these latencies. + +Signed-off-by: Eric Yang <Eric.Yang2@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 16 ++++++++++++---- + .../drm/amd/display/dc/dcn21/dcn21_resource.c | 15 ++++++++++++--- + drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 ++ + 3 files changed, 26 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +index 790a2d211bd6..841095d09d3c 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +@@ -523,25 +523,33 @@ struct clk_bw_params rn_bw_params = { + { + .wm_inst = WM_A, + .wm_type = WM_TYPE_PSTATE_CHG, +- .pstate_latency_us = 23.84, ++ .pstate_latency_us = 11.72, ++ .sr_exit_time_us = 6.09, ++ .sr_enter_plus_exit_time_us = 7.14, + .valid = true, + }, + { + .wm_inst = WM_B, + .wm_type = WM_TYPE_PSTATE_CHG, +- .pstate_latency_us = 23.84, ++ .pstate_latency_us = 11.72, ++ .sr_exit_time_us = 10.12, ++ .sr_enter_plus_exit_time_us = 11.48, + .valid = true, + }, + { + .wm_inst = WM_C, + .wm_type = WM_TYPE_PSTATE_CHG, +- .pstate_latency_us = 23.84, ++ .pstate_latency_us = 11.72, ++ .sr_exit_time_us = 10.12, ++ .sr_enter_plus_exit_time_us = 11.48, + .valid = true, + }, + { + .wm_inst = WM_D, + .wm_type = WM_TYPE_PSTATE_CHG, +- .pstate_latency_us = 23.84, ++ .pstate_latency_us = 11.72, ++ .sr_exit_time_us = 10.12, ++ .sr_enter_plus_exit_time_us = 11.48, + .valid = true, + }, + }, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +index 260471ac20c2..94a5611972cc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +@@ -972,6 +972,8 @@ static void calculate_wm_set_for_vlevel( + pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; + + dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; ++ dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; ++ dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; + + wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; + wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; +@@ -989,14 +991,21 @@ static void calculate_wm_set_for_vlevel( + + static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) + { ++ int i; ++ + kernel_fpu_begin(); + if (dc->bb_overrides.sr_exit_time_ns) { +- bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; ++ for (i = 0; i < WM_SET_COUNT; i++) { ++ dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = ++ dc->bb_overrides.sr_exit_time_ns / 1000.0; ++ } + } + + if (dc->bb_overrides.sr_enter_plus_exit_time_ns) { +- bb->sr_enter_plus_exit_time_us = +- dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; ++ for (i = 0; i < WM_SET_COUNT; i++) { ++ dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = ++ dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; ++ } + } + + if (dc->bb_overrides.urgent_latency_ns) { +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +index 4e18e77dcf42..026e6a2a2c44 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +@@ -69,6 +69,8 @@ struct wm_range_table_entry { + unsigned int wm_inst; + unsigned int wm_type; + double pstate_latency_us; ++ double sr_exit_time_us; ++ double sr_enter_plus_exit_time_us; + bool valid; + }; + +-- +2.17.1 + |