diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3247-drm-amdgpu-initialize-new-parameters-and-functions-f.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3247-drm-amdgpu-initialize-new-parameters-and-functions-f.patch | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3247-drm-amdgpu-initialize-new-parameters-and-functions-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3247-drm-amdgpu-initialize-new-parameters-and-functions-f.patch new file mode 100644 index 00000000..8e54744a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3247-drm-amdgpu-initialize-new-parameters-and-functions-f.patch @@ -0,0 +1,86 @@ +From b31dcf8604c639c2d7c2db273b8fb0c37ae0922f Mon Sep 17 00:00:00 2001 +From: Tao Zhou <tao.zhou1@amd.com> +Date: Mon, 29 Jul 2019 14:28:35 +0800 +Subject: [PATCH 3247/4256] drm/amdgpu: initialize new parameters and functions + for amdgpu_umc structure + +add initialization for new members of amdgpu_umc structure + +Signed-off-by: Tao Zhou <tao.zhou1@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++++-- + drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 +++++++++- + drivers/gpu/drm/amd/amdgpu/umc_v6_1.h | 3 +++ + 3 files changed, 17 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index 7f4da9254dfb..2f72968ec566 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -628,8 +628,11 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) + { + switch (adev->asic_type) { + case CHIP_VEGA20: +- adev->umc.max_ras_err_cnt_per_query = +- UMC_V6_1_UMC_INSTANCE_NUM * UMC_V6_1_CHANNEL_INSTANCE_NUM; ++ adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; ++ adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; ++ adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; ++ adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET; ++ adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; + adev->umc.funcs = &umc_v6_1_funcs; + break; + default: +diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c +index 035e4fea472c..9ba015d7eb57 100644 +--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c ++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c +@@ -41,7 +41,7 @@ + /* offset in 256B block */ + #define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL) + +-static uint32_t ++const uint32_t + umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = { + {2, 18, 11, 27}, {4, 20, 13, 29}, + {1, 17, 8, 24}, {7, 23, 14, 30}, +@@ -235,7 +235,15 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev, + umc_v6_1_disable_umc_index_mode(adev); + } + ++static void umc_v6_1_ras_init(struct amdgpu_device *adev) ++{ ++ ++} ++ + const struct amdgpu_umc_funcs umc_v6_1_funcs = { ++ .ras_init = umc_v6_1_ras_init, + .query_ras_error_count = umc_v6_1_query_ras_error_count, + .query_ras_error_address = umc_v6_1_query_ras_error_address, ++ .enable_umc_index_mode = umc_v6_1_enable_umc_index_mode, ++ .disable_umc_index_mode = umc_v6_1_disable_umc_index_mode, + }; +diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h +index bddaf14a77f9..ad4598c0e495 100644 +--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h ++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h +@@ -24,6 +24,7 @@ + #define __UMC_V6_1_H__ + + #include "soc15_common.h" ++#include "amdgpu.h" + + /* HBM Memory Channel Width */ + #define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH 128 +@@ -37,5 +38,7 @@ + #define UMC_V6_1_PER_CHANNEL_OFFSET 0x800 + + extern const struct amdgpu_umc_funcs umc_v6_1_funcs; ++extern const uint32_t ++ umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM]; + + #endif +-- +2.17.1 + |