diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3155-drm-amdgpu-move-PD-PT-address-calculation-into-backe.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3155-drm-amdgpu-move-PD-PT-address-calculation-into-backe.patch | 216 |
1 files changed, 216 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3155-drm-amdgpu-move-PD-PT-address-calculation-into-backe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3155-drm-amdgpu-move-PD-PT-address-calculation-into-backe.patch new file mode 100644 index 00000000..a85ac715 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3155-drm-amdgpu-move-PD-PT-address-calculation-into-backe.patch @@ -0,0 +1,216 @@ +From c2ebd985767479e7f7d74b556840d264021745f0 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Tue, 16 Jan 2018 16:54:25 +0100 +Subject: [PATCH 3155/4131] drm/amdgpu: move PD/PT address calculation into + backend function +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This way we can better handle the differences for CPU based updates. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 79 +++++++++++++--------------------- + 1 file changed, 29 insertions(+), 50 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +index eb0a055..6670595 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -75,7 +75,8 @@ struct amdgpu_pte_update_params { + /* indirect buffer to fill with commands */ + struct amdgpu_ib *ib; + /* Function which actually does the update */ +- void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, ++ void (*func)(struct amdgpu_pte_update_params *params, ++ struct amdgpu_bo *bo, uint64_t pe, + uint64_t addr, unsigned count, uint32_t incr, + uint64_t flags); + /* The next two are used during VM update by CPU +@@ -583,6 +584,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, + * amdgpu_vm_do_set_ptes - helper to call the right asic function + * + * @params: see amdgpu_pte_update_params definition ++ * @bo: PD/PT to update + * @pe: addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update +@@ -593,10 +595,12 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, + * to setup the page table using the DMA. + */ + static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, ++ struct amdgpu_bo *bo, + uint64_t pe, uint64_t addr, + unsigned count, uint32_t incr, + uint64_t flags) + { ++ pe += amdgpu_bo_gpu_offset(bo); + trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); + + if (count < 3) { +@@ -613,6 +617,7 @@ static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, + * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART + * + * @params: see amdgpu_pte_update_params definition ++ * @bo: PD/PT to update + * @pe: addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update +@@ -622,13 +627,14 @@ static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, + * Traces the parameters and calls the DMA function to copy the PTEs. + */ + static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, ++ struct amdgpu_bo *bo, + uint64_t pe, uint64_t addr, + unsigned count, uint32_t incr, + uint64_t flags) + { + uint64_t src = (params->src + (addr >> 12) * 8); + +- ++ pe += amdgpu_bo_gpu_offset(bo); + trace_amdgpu_vm_copy_ptes(pe, src, count); + + amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); +@@ -662,6 +668,7 @@ static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) + * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU + * + * @params: see amdgpu_pte_update_params definition ++ * @bo: PD/PT to update + * @pe: kmap addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update +@@ -671,6 +678,7 @@ static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) + * Write count number of PT/PD entries directly. + */ + static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, ++ struct amdgpu_bo *bo, + uint64_t pe, uint64_t addr, + unsigned count, uint32_t incr, + uint64_t flags) +@@ -678,6 +686,8 @@ static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, + unsigned int i; + uint64_t value; + ++ pe += (unsigned long)amdgpu_bo_kptr(bo); ++ + trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); + + for (i = 0; i < count; i++) { +@@ -719,8 +729,7 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params, + struct amdgpu_vm_pt *parent, + struct amdgpu_vm_pt *entry) + { +- struct amdgpu_bo *bo = entry->base.bo, *shadow = NULL, *pbo; +- uint64_t pd_addr, shadow_addr = 0; ++ struct amdgpu_bo *bo = parent->base.bo, *pbo; + uint64_t pde, pt, flags; + unsigned level; + +@@ -728,29 +737,17 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params, + if (entry->huge) + return; + +- if (vm->use_cpu_for_update) { +- pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo); +- } else { +- pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); +- shadow = parent->base.bo->shadow; +- if (shadow) +- shadow_addr = amdgpu_bo_gpu_offset(shadow); +- } +- +- for (level = 0, pbo = parent->base.bo->parent; pbo; ++level) ++ for (level = 0, pbo = bo->parent; pbo; ++level) + pbo = pbo->parent; + + level += params->adev->vm_manager.root_level; +- pt = amdgpu_bo_gpu_offset(bo); ++ pt = amdgpu_bo_gpu_offset(entry->base.bo); + flags = AMDGPU_PTE_VALID; + amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags); +- if (shadow) { +- pde = shadow_addr + (entry - parent->entries) * 8; +- params->func(params, pde, pt, 1, 0, flags); +- } +- +- pde = pd_addr + (entry - parent->entries) * 8; +- params->func(params, pde, pt, 1, 0, flags); ++ pde = (entry - parent->entries) * 8; ++ if (bo->shadow) ++ params->func(params, bo->shadow, pde, pt, 1, 0, flags); ++ params->func(params, bo, pde, pt, 1, 0, flags); + } + + /* +@@ -951,7 +948,7 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, + unsigned nptes, uint64_t dst, + uint64_t flags) + { +- uint64_t pd_addr, pde; ++ uint64_t pde; + + /* In the case of a mixed PT the PDE must point to it*/ + if (p->adev->asic_type >= CHIP_VEGA10 && !p->src && +@@ -974,18 +971,10 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, + entry->huge = true; + amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags); + +- if (p->func == amdgpu_vm_cpu_set_ptes) { +- pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo); +- } else { +- if (parent->base.bo->shadow) { +- pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow); +- pde = pd_addr + (entry - parent->entries) * 8; +- p->func(p, pde, dst, 1, 0, flags); +- } +- pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); +- } +- pde = pd_addr + (entry - parent->entries) * 8; +- p->func(p, pde, dst, 1, 0, flags); ++ pde = (entry - parent->entries) * 8; ++ if (parent->base.bo->shadow) ++ p->func(p, parent->base.bo->shadow, pde, dst, 1, 0, flags); ++ p->func(p, parent->base.bo, pde, dst, 1, 0, flags); + } + + /** +@@ -1011,7 +1000,6 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, + uint64_t addr, pe_start; + struct amdgpu_bo *pt; + unsigned nptes; +- bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes); + + /* walk over the address space and update the page tables */ + for (addr = start; addr < end; addr += nptes, +@@ -1034,20 +1022,11 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, + continue; + + pt = entry->base.bo; +- if (use_cpu_update) { +- pe_start = (unsigned long)amdgpu_bo_kptr(pt); +- } else { +- if (pt->shadow) { +- pe_start = amdgpu_bo_gpu_offset(pt->shadow); +- pe_start += (addr & mask) * 8; +- params->func(params, pe_start, dst, nptes, +- AMDGPU_GPU_PAGE_SIZE, flags); +- } +- pe_start = amdgpu_bo_gpu_offset(pt); +- } +- +- pe_start += (addr & mask) * 8; +- params->func(params, pe_start, dst, nptes, ++ pe_start = (addr & mask) * 8; ++ if (pt->shadow) ++ params->func(params, pt->shadow, pe_start, dst, nptes, ++ AMDGPU_GPU_PAGE_SIZE, flags); ++ params->func(params, pt, pe_start, dst, nptes, + AMDGPU_GPU_PAGE_SIZE, flags); + } + +-- +2.7.4 + |