diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0620-drm-amd-display-hwseq-init-sequence-update.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0620-drm-amd-display-hwseq-init-sequence-update.patch | 197 |
1 files changed, 197 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0620-drm-amd-display-hwseq-init-sequence-update.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0620-drm-amd-display-hwseq-init-sequence-update.patch new file mode 100644 index 00000000..bdce58c8 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0620-drm-amd-display-hwseq-init-sequence-update.patch @@ -0,0 +1,197 @@ +From 7c1151b10712b0eacf437781edddad6531e8f6bd Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Fri, 7 Jul 2017 17:21:45 -0400 +Subject: [PATCH 0620/4131] drm/amd/display: hwseq init sequence update + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 8 +++- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 51 +++++----------------- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 +- + .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 1 - + 4 files changed, 20 insertions(+), 42 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index 4da9142..7e1d46f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -216,6 +216,11 @@ struct dce_hwseq_registers { + uint32_t DCCG_GATE_DISABLE_CNTL; + uint32_t DCCG_GATE_DISABLE_CNTL2; + uint32_t DCFCLK_CNTL; ++ uint32_t MICROSECOND_TIME_BASE_DIV; ++ uint32_t MILLISECOND_TIME_BASE_DIV; ++ uint32_t DISPCLK_FREQ_CHANGE_CNTL; ++ uint32_t RBBMIF_TIMEOUT_DIS; ++ uint32_t RBBMIF_TIMEOUT_DIS_2; + #endif + }; + /* set field name */ +@@ -378,7 +383,8 @@ struct dce_hwseq_registers { + type DOMAIN5_PGFSM_PWR_STATUS; \ + type DOMAIN6_PGFSM_PWR_STATUS; \ + type DOMAIN7_PGFSM_PWR_STATUS; \ +- type DCFCLK_GATE_DIS; ++ type DCFCLK_GATE_DIS; \ ++ type DCHUBBUB_GLOBAL_TIMER_REFDIV; + #endif + + struct dce_hwseq_shift { +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index fc46c84..eca0d53 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -24,11 +24,9 @@ + */ + + #include "dm_services.h" +-#include "dc.h" +-#include "core_dc.h" + #include "core_types.h" +-#include "core_status.h" + #include "resource.h" ++#include "custom_float.h" + #include "dcn10_hw_sequencer.h" + #include "dce110/dce110_hw_sequencer.h" + #include "dce/dce_hwseq.h" +@@ -39,11 +37,10 @@ + #include "timing_generator.h" + #include "opp.h" + #include "ipp.h" +-#include "dc_bios_types.h" ++#include "mpc.h" + #include "raven1/DCN/dcn_1_0_offset.h" + #include "raven1/DCN/dcn_1_0_sh_mask.h" + #include "vega10/soc15ip.h" +-#include "custom_float.h" + #include "reg_helper.h" + + #define CTX \ +@@ -219,31 +216,15 @@ static void bios_golden_init(struct core_dc *dc) + } + } + +-/* +- * This should be done within BIOS, we are doing it for maximus only +- */ +-static void dchubup_setup_timer(struct dce_hwseq *hws) +-{ +- REG_WRITE(REFCLK_CNTL, 0); +- +- REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); +-} +- +-static void init_hw(struct core_dc *dc) ++static void dcn10_init_hw(struct core_dc *dc) + { + int i; +- struct transform *xfm; +- struct abm *abm; ++ struct abm *abm = dc->res_pool->abm; + struct dce_hwseq *hws = dc->hwseq; + +-#if 1 + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { +- dchubup_setup_timer(dc->hwseq); +- +- /* TODO: dchubp_map_fb_to_mc will be moved to dchub interface +- * between dc and kmd +- */ +- /*dchubp_map_fb_to_mc(dc->hwseq);*/ ++ REG_WRITE(REFCLK_CNTL, 0); ++ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); + REG_WRITE(DIO_MEM_PWR_CTRL, 0); + + if (!dc->public.debug.disable_clock_gate) { +@@ -259,15 +240,9 @@ static void init_hw(struct core_dc *dc) + return; + } + /* end of FPGA. Below if real ASIC */ +-#endif + + bios_golden_init(dc); + +- for (i = 0; i < dc->res_pool->pipe_count; i++) { +- xfm = dc->res_pool->transforms[i]; +- xfm->funcs->transform_reset(xfm); +- } +- + for (i = 0; i < dc->link_count; i++) { + /* Power up AND update implementation according to the + * required signal (which may be different from the +@@ -279,12 +254,12 @@ static void init_hw(struct core_dc *dc) + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { +- struct timing_generator *tg = +- dc->res_pool->timing_generators[i]; +- struct mpcc *mpcc = +- dc->res_pool->mpcc[i]; ++ struct transform *xfm = dc->res_pool->transforms[i]; ++ struct timing_generator *tg = dc->res_pool->timing_generators[i]; ++ struct mpcc *mpcc = dc->res_pool->mpcc[i]; + struct mpcc_cfg mpcc_cfg; + ++ xfm->funcs->transform_reset(xfm); + mpcc_cfg.opp_id = 0xf; + mpcc_cfg.top_dpp_id = 0xf; + mpcc_cfg.bot_mpcc_id = 0xf; +@@ -305,7 +280,6 @@ static void init_hw(struct core_dc *dc) + audio->funcs->hw_init(audio); + } + +- abm = dc->res_pool->abm; + if (abm != NULL) { + abm->funcs->init_backlight(abm); + abm->funcs->abm_init(abm); +@@ -1859,7 +1833,7 @@ static bool dcn10_dummy_display_power_gating( + static const struct hw_sequencer_funcs dcn10_funcs = { + .program_gamut_remap = program_gamut_remap, + .program_csc_matrix = program_csc_matrix, +- .init_hw = init_hw, ++ .init_hw = dcn10_init_hw, + .apply_ctx_to_hw = dce110_apply_ctx_to_hw, + .apply_ctx_for_surface = dcn10_apply_ctx_for_surface, + .set_plane_config = set_plane_config, +@@ -1888,9 +1862,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = { + }; + + +-bool dcn10_hw_sequencer_construct(struct core_dc *dc) ++void dcn10_hw_sequencer_construct(struct core_dc *dc) + { + dc->hwss = dcn10_funcs; +- return true; + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +index c3aff2e..28218dc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +@@ -30,7 +30,7 @@ + + struct core_dc; + +-bool dcn10_hw_sequencer_construct(struct core_dc *dc); ++void dcn10_hw_sequencer_construct(struct core_dc *dc); + extern void fill_display_configs( + const struct validate_context *context, + struct dm_pp_display_configuration *pp_display_cfg); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +index b7ecfad..4e723a0 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +@@ -403,7 +403,6 @@ static void min10_program_requestor( + struct mem_input *mem_input, + struct _vcs_dpi_display_rq_regs_st *rq_regs) + { +- + struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + + REG_UPDATE(HUBPRET_CONTROL, +-- +2.7.4 + |