diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0449-drm-amd-display-Clean-up-indentation-in-dce120_tg_se.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0449-drm-amd-display-Clean-up-indentation-in-dce120_tg_se.patch | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0449-drm-amd-display-Clean-up-indentation-in-dce120_tg_se.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0449-drm-amd-display-Clean-up-indentation-in-dce120_tg_se.patch new file mode 100644 index 00000000..47cbeec8 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0449-drm-amd-display-Clean-up-indentation-in-dce120_tg_se.patch @@ -0,0 +1,43 @@ +From 226bea1e158e813b11b5b961182f8e3317d0d41f Mon Sep 17 00:00:00 2001 +From: Tom St Denis <tom.stdenis@amd.com> +Date: Tue, 16 May 2017 10:22:03 -0400 +Subject: [PATCH 0449/4131] drm/amd/display: Clean up indentation in + dce120_tg_set_blank() + +Signed-off-by: Tom St Denis <tom.stdenis@amd.com> +Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/display/dc/dce120/dce120_timing_generator.c | 16 +++++----------- + 1 file changed, 5 insertions(+), 11 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +index 1e2843e..c208196 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +@@ -768,17 +768,11 @@ void dce120_tg_set_blank(struct timing_generator *tg, + CRTC0_CRTC_DOUBLE_BUFFER_CONTROL, + CRTC_BLANK_DATA_DOUBLE_BUFFER_EN, 0); + +- if (enable_blanking) { +- CRTC_REG_SET( +- CRTC0_CRTC_BLANK_CONTROL, +- CRTC_BLANK_DATA_EN, 1); +- +- } else +- dm_write_reg_soc15( +- tg->ctx, +- mmCRTC0_CRTC_BLANK_CONTROL, +- tg110->offsets.crtc, +- 0); ++ if (enable_blanking) ++ CRTC_REG_SET(CRTC0_CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); ++ else ++ dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL, ++ tg110->offsets.crtc, 0); + } + + bool dce120_tg_validate_timing(struct timing_generator *tg, +-- +2.7.4 + |