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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1449-drm-amd-display-use-odm-combine-for-YCbCr420-timing-.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1449-drm-amd-display-use-odm-combine-for-YCbCr420-timing-.patch148
1 files changed, 148 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1449-drm-amd-display-use-odm-combine-for-YCbCr420-timing-.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1449-drm-amd-display-use-odm-combine-for-YCbCr420-timing-.patch
new file mode 100644
index 00000000..ef438a37
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1449-drm-amd-display-use-odm-combine-for-YCbCr420-timing-.patch
@@ -0,0 +1,148 @@
+From c5c7d22d366f2eb7bb57c8e9d21da6f55f07819a Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Mon, 13 Jan 2020 17:05:42 -0500
+Subject: [PATCH 1449/1453] drm/amd/display: use odm combine for YCbCr420
+ timing with h_active greater than 4096
+
+[why]
+FMT has limitation to support YCbCr420 with h_active greater than 4096.
+
+[how]
+Use odm combine to overcome the limitation.
+
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../dc/dml/dcn20/display_mode_vba_20.c | 19 ++++++++++-----
+ .../dc/dml/dcn20/display_mode_vba_20v2.c | 24 ++++++++++++-------
+ .../dc/dml/dcn21/display_mode_vba_21.c | 24 ++++++++++++-------
+ 3 files changed, 45 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+index e7a8ac7a1f22..45f028986a8d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+@@ -38,6 +38,7 @@
+
+ #define BPP_INVALID 0
+ #define BPP_BLENDED_PIPE 0xffffffff
++#define DCN20_MAX_420_IMAGE_WIDTH 4096
+
+ static double adjust_ReturnBW(
+ struct display_mode_lib *mode_lib,
+@@ -3894,13 +3895,19 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
+ && i == mode_lib->vba.soc.num_states)
+ mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+- if (mode_lib->vba.ODMCapability == false || mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
+- locals->ODMCombineEnablePerState[i][k] = false;
+- mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
+- } else {
+- locals->ODMCombineEnablePerState[i][k] = true;
+- mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
++
++ locals->ODMCombineEnablePerState[i][k] = false;
++ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
++ if (mode_lib->vba.ODMCapability) {
++ if (locals->PlaneRequiredDISPCLKWithoutODMCombine > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
++ locals->ODMCombineEnablePerState[i][k] = true;
++ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
++ } else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
++ locals->ODMCombineEnablePerState[i][k] = true;
++ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
++ }
+ }
++
+ if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
+ && locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]
+ && locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+index 22f3b5a4b3b9..485a9c62ec58 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+@@ -39,6 +39,7 @@
+ #define BPP_INVALID 0
+ #define BPP_BLENDED_PIPE 0xffffffff
+ #define DCN20_MAX_DSC_IMAGE_WIDTH 5184
++#define DCN20_MAX_420_IMAGE_WIDTH 4096
+
+ static double adjust_ReturnBW(
+ struct display_mode_lib *mode_lib,
+@@ -3935,15 +3936,22 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
+ && i == mode_lib->vba.soc.num_states)
+ mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+- if (mode_lib->vba.ODMCapability == false ||
+- (locals->PlaneRequiredDISPCLKWithoutODMCombine <= MaxMaxDispclkRoundedDown
+- && (!locals->DSCEnabled[k] || locals->HActive[k] <= DCN20_MAX_DSC_IMAGE_WIDTH))) {
+- locals->ODMCombineEnablePerState[i][k] = false;
+- mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
+- } else {
+- locals->ODMCombineEnablePerState[i][k] = true;
+- mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
++
++ locals->ODMCombineEnablePerState[i][k] = false;
++ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
++ if (mode_lib->vba.ODMCapability) {
++ if (locals->PlaneRequiredDISPCLKWithoutODMCombine > MaxMaxDispclkRoundedDown) {
++ locals->ODMCombineEnablePerState[i][k] = true;
++ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
++ } else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN20_MAX_DSC_IMAGE_WIDTH)) {
++ locals->ODMCombineEnablePerState[i][k] = true;
++ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
++ } else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
++ locals->ODMCombineEnablePerState[i][k] = true;
++ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
++ }
+ }
++
+ if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
+ && locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]
+ && locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+index e7842bbf4eb9..da95259060f8 100755
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+@@ -66,6 +66,7 @@ typedef struct {
+ #define BPP_INVALID 0
+ #define BPP_BLENDED_PIPE 0xffffffff
+ #define DCN21_MAX_DSC_IMAGE_WIDTH 5184
++#define DCN21_MAX_420_IMAGE_WIDTH 4096
+
+ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
+ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
+@@ -3972,15 +3973,22 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
+ && i == mode_lib->vba.soc.num_states)
+ mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+- if (mode_lib->vba.ODMCapability == false ||
+- (locals->PlaneRequiredDISPCLKWithoutODMCombine <= MaxMaxDispclkRoundedDown
+- && (!locals->DSCEnabled[k] || locals->HActive[k] <= DCN21_MAX_DSC_IMAGE_WIDTH))) {
+- locals->ODMCombineEnablePerState[i][k] = false;
+- mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
+- } else {
+- locals->ODMCombineEnablePerState[i][k] = true;
+- mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
++
++ locals->ODMCombineEnablePerState[i][k] = false;
++ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
++ if (mode_lib->vba.ODMCapability) {
++ if (locals->PlaneRequiredDISPCLKWithoutODMCombine > MaxMaxDispclkRoundedDown) {
++ locals->ODMCombineEnablePerState[i][k] = true;
++ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
++ } else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN21_MAX_DSC_IMAGE_WIDTH)) {
++ locals->ODMCombineEnablePerState[i][k] = true;
++ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
++ } else if (locals->HActive[k] > DCN21_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
++ locals->ODMCombineEnablePerState[i][k] = true;
++ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
++ }
+ }
++
+ if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
+ && locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]
+ && locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-06-15 06:10:32 +0000